采用双锁相环的低功耗RISC微处理器，采用0.13 /spl mu/m SOI技术，采用铜互连和低k BEOL介电

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992979

S. Geissler, D. Appenzeller, E. Cohen, S. Charlebois, P. Kartschoke, P. McCormick, N. Rohrer, G. Salem, P. Sandon, B. Singer, T. von Reyn, J. Zimmerman

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引用次数: 27

摘要

为移动应用实现时钟频率> 1ghz的微处理器需要解决方案来保持较长的电池寿命。讨论了多个锁相环之间动态频率切换的电路和架构解决方案、直流功率降低方法以及低k介电对时序和功率的影响。

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A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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