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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)最新文献

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A 10 /spl mu/V-offset 8 kHz bandwidth 4/sup th/-order chopped /spl Sigma//spl Delta/ A/D converter for battery management 用于电池管理的10 /spl mu/ v偏置8 kHz带宽4/sup /阶斩波/spl Sigma//spl Delta/ A/D转换器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993095
P. Blanken, S. Menten
{"title":"A 10 /spl mu/V-offset 8 kHz bandwidth 4/sup th/-order chopped /spl Sigma//spl Delta/ A/D converter for battery management","authors":"P. Blanken, S. Menten","doi":"10.1109/ISSCC.2002.993095","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993095","url":null,"abstract":"A chopped 4/sup th-/order continuous-time 1 bit /spl Sigma//spl Delta/ A/D converter with 10 /spl mu/V offset and 8 kHz bandwidth has been designed for battery current measurement. Chopping at 16 kHz, the circuit has a 0.1 V input range, a 68 dB SNR, and a 1 MHz output bit rate. Area is 0.45x0.4 mm in 0.35 /spl mu/m CMOS. Current consumption is 30 /spl mu/A at 2.5-4 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The clock distribution of the Power4 microprocessor Power4微处理器的时钟分布
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992162
P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, A. Mulé
{"title":"The clock distribution of the Power4 microprocessor","authors":"P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, A. Mulé","doi":"10.1109/ISSCC.2002.992162","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992162","url":null,"abstract":"The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132591283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
A CMOS broadband tuner IC 一种CMOS宽带调谐器IC
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993101
L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell
{"title":"A CMOS broadband tuner IC","authors":"L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell","doi":"10.1109/ISSCC.2002.993101","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993101","url":null,"abstract":"A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports 一个包内存集成的44gb /s交换处理器，带有10gb端口和12gb端口
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992096
M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih
{"title":"A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports","authors":"M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih","doi":"10.1109/ISSCC.2002.992096","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992096","url":null,"abstract":"A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127359314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.5 Mpixel imager with localized hole-modulation method 一种150万像素的局部空穴调制成像仪
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992929
T. Miida, K. Kawajiri, H. Terakago, T. Endo, T. Okazaki, S. Yamamoto, A. Nishimura
{"title":"A 1.5 Mpixel imager with localized hole-modulation method","authors":"T. Miida, K. Kawajiri, H. Terakago, T. Endo, T. Okazaki, S. Yamamoto, A. Nishimura","doi":"10.1109/ISSCC.2002.992929","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992929","url":null,"abstract":"A 1.5 Mpixel imager with 4.2 /spl mu/m square pixel is composed of a single MOSFET and a pinned photodiode. A localized high-density p-region near the source of the MOSFET converts the accumulated hole number to source voltage. Low random noise, low dark signal, high sensitivity with good color reproduction and resolution are achieved.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126971085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends 用于集成ADSL模拟前端的嵌入式数字自适应偏置算法的0.5/spl mu/m CMOS低失真低功耗线路驱动器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992243
M. Ingels, S. Bojja, P. Wouters
{"title":"A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends","authors":"M. Ingels, S. Bojja, P. Wouters","doi":"10.1109/ISSCC.2002.992243","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992243","url":null,"abstract":"A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126849388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 34 word/spl times/64 b 10 R/6 W write-through self timed dual-supply-voltage register file 一个34字/倍/ 64b / 10r / 6w的自定时双电源电压寄存器文件
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993109
N. Tzartzanis, W. Walker, H. Nguyen, A. Inoue
{"title":"A 34 word/spl times/64 b 10 R/6 W write-through self timed dual-supply-voltage register file","authors":"N. Tzartzanis, W. Walker, H. Nguyen, A. Inoue","doi":"10.1109/ISSCC.2002.993109","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993109","url":null,"abstract":"A register file leverages from a replica-based control unit to improve reliability, operate in a wide voltage range, and support two supply voltages. The main power supply can be stepped down to reduce power, or shut off for sleep mode. Access time is 1.4 ns and power dissipation is 220 mW at 500 MHz in 1.2 V, 0.11 /spl mu/m CMOS.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115819411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 500 dpi 224/spl times/256-pixel single-chip fingerprint identification LSI with pixel-parallel image enhancement and rotation schemes 具有像素并行图像增强和旋转方案的500 dpi 224/spl倍/256像素单片指纹识别LSI
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993078
S. Shigematsu, K. Fujii, H. Morimura, T. Hatano, M. Nakanishi, T. Adachi, N. Ikeda, T. Shimamura, Katsuyuki Machida, Y. Okazaki, H. Kyuragi
{"title":"A 500 dpi 224/spl times/256-pixel single-chip fingerprint identification LSI with pixel-parallel image enhancement and rotation schemes","authors":"S. Shigematsu, K. Fujii, H. Morimura, T. Hatano, M. Nakanishi, T. Adachi, N. Ikeda, T. Shimamura, Katsuyuki Machida, Y. Okazaki, H. Kyuragi","doi":"10.1109/ISSCC.2002.993078","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993078","url":null,"abstract":"A 500-dpi 224×256-pixel single-chip fingerprint identification LSI adapts the sensing circuit to a finger and performs pixel-parallel image processing and rotation in a pixel array. A test chip achieves 2 ms 10 mW sensing, 41 ms 19.2 mW identification, and practical identification accuracy at 2.5 V, 5 MHz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A CMOS IF sampling circuit with reduced aliasing for wireless applications 用于无线应用的减少混叠的CMOS中频采样电路
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993103
S. Levantino, C. Samori, M. Banu, Jack Glas, V. Boccuzzi
{"title":"A CMOS IF sampling circuit with reduced aliasing for wireless applications","authors":"S. Levantino, C. Samori, M. Banu, Jack Glas, V. Boccuzzi","doi":"10.1109/ISSCC.2002.993103","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993103","url":null,"abstract":"An IF-sampling technique rejects even-order alias channels. A 0.25 /spl mu/m CMOS test chip demonstrates 27 dB anti-aliasing rejection, 70 dB dynamic range, and -121 dBm/Hz noise floor, for a 377 MHz IF GSM signal, with 52 MHz sampling rate.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions 具有SIMD架构和快速3D功能的双问题浮点协处理器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993108
R. Rogenmoser, L. O'Donnell, S. Nishimoto
{"title":"A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions","authors":"R. Rogenmoser, L. O'Donnell, S. Nishimoto","doi":"10.1109/ISSCC.2002.993108","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993108","url":null,"abstract":"A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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