A CMOS broadband tuner IC

Abstract

A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.