2013 IEEE 19th International On-Line Testing Symposium (IOLTS)最新文献_第5页

Video decoder monitoring using non-linear regression 视频解码器的非线性回归监控

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604073

Brice Ekobo Akoa, E. Simeu, F. Lebowsky

引用次数: 8

The functional and performance tolerance of GPUs to permanent faults in registers gpu对寄存器中永久故障的功能和性能容忍度

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604089

Sotiris Tselonis, Vasilis Dimitsas, D. Gizopoulos

{"title":"The functional and performance tolerance of GPUs to permanent faults in registers","authors":"Sotiris Tselonis, Vasilis Dimitsas, D. Gizopoulos","doi":"10.1109/IOLTS.2013.6604089","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604089","url":null,"abstract":"Massively parallel many-core Graphics Processing Unit (GPU) architectures offer significant performance speedup in workloads with thread-level parallelism compared to contemporary multicore CPUs. For this reason, general-purpose computing using GPUs (GPGPU) is a rapidly expanding research direction in different contexts. Unlike graphics processing, GPGPU computing requires reliable operation in the presence of hardware faults whose occurrence probabilities in current and forthcoming advanced manufacturing technologies will be significant. In this paper, we focus on the aspect of tolerance of GPUs to permanent faults in their most critical storage elements: register files. By performing a comprehensive fault injection campaign on a cycle-accurate GPGPU architectural simulator, we first evaluate and classify the behavior of NVIDIA GPU CUDA kernels in the presence of permanent faults in registers. Moreover, we analyze the performance tolerance of GPUs when they operate in degraded mode (less hardware resources, less thread-level parallelism) due to the presence of multiple permanent faults in the registers of their streaming multiprocessors. Our findings confirm the intuitively expected tolerance of these architectures to faults and also quantify it in different configurations and modes.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Accurate alpha soft error rate evaluation in SRAM memories SRAM存储器中精确的alpha软错误率评估

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604080

S. Bota, G. Torrens, I. D. Paúl, B. Alorda, L. A. Segura

引用次数: 2

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs 分层硬件检查点加速基于sram的fpga的故障恢复

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604078

En-Chung Yang, Keheng Huang, Yu Hu, Xiaowei Li, Jian Gong, Hongjin Liu, Bo Liu

{"title":"HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs","authors":"En-Chung Yang, Keheng Huang, Yu Hu, Xiaowei Li, Jian Gong, Hongjin Liu, Bo Liu","doi":"10.1109/IOLTS.2013.6604078","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604078","url":null,"abstract":"As the feature size shrinks to the nanometer scale, SRAM-based FPGAs are increasingly vulnerable to soft errors. Checkpointing is an effective fault recovery technique that can restore the faulty system to its previous fault free state. Since the function of the system needs to be suspended during checkpoint saving and checkpoint restoring, so the Mean Time to Repair (MTTR) of the system is critical to the system performance. In this work, we propose a hierarchical hardware checkpointing (HHC) technique that contains a high-speed on-chip checkpoint and a low-speed off-chip checkpoint to accelerate fault recovery for SRAM-based FPGAs. Most of single event effect (SEE) faults can be recovered by the high-speed on-chip checkpoint, which significantly reduces the MTTR of the system. The memory resource occupation of the on-chip checkpoint is low because HHC only stores the logic states of user bits and check information for configuration bits. Experimental results show that, compared with traditional off-chip checkpoint strategies, the proposed technique can reduce the MTTR of the system by 94.30%. In addition, the memory resource occupation is 11.11% of FPGAs, a little high but can be further optimized.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A low-cost input vector monitoring concurrent BIST scheme 一种低成本输入向量监测并行BIST方案

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604074

I. Voyiatzis, C. Efstathiou, C. Sgouropoulou

引用次数: 0

Scan attack in presence of mode-reset countermeasure 扫描攻击存在模式重置对抗

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604086

Subidh Ali, S. Saeed, O. Sinanoglu, R. Karri

引用次数: 18

A radiation tolerant and self-repair memory cell 一种耐辐射和自我修复的记忆细胞

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604081

Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, K. Pekmestzi

引用次数: 2

A post-deployment IC trust evaluation architecture 部署后IC信任评估架构

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604083

Yier Jin, Dzmitry Maliuk, Y. Makris

{"title":"A post-deployment IC trust evaluation architecture","authors":"Yier Jin, Dzmitry Maliuk, Y. Makris","doi":"10.1109/IOLTS.2013.6604083","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604083","url":null,"abstract":"The use of side-channel parametric measurements along with statistical analysis methods for detecting hardware Trojans in fabricated integrated circuits has been studied extensively in recent years, initially for digital designs but recently also for their analog/RF counterparts. Such post-fabrication trust evaluation methods, however, are unable to detect dormant hardware Trojans which are activated after a circuit is deployed in its field of operation. For the latter, an on-chip trust evaluation method is required. To this end, we present a general architecture for post-deployment trust evaluation based on on-chip classifiers. Specifically, we discuss the design of an on-chip analog neural network which can be trained to distinguish trusted from untrusted circuit functionality based on simple measurements obtained via on-chip measurement acquisition sensors. The proposed method is demonstrated using a Trojan-free and two Trojan-infested variants of a wireless cryptographic IC design, as well as a fabricated programmable neural network experimentation chip. As corroborated by the obtained experimental results, two current measurements suffice for the on-chip classifier to effectively assess trustworthiness and, thereby, detect hardware Trojans that are activated after chip deployment.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Hierarchical RTL-based combinatorial SER estimation 基于分层rtl的组合SER估计

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604065

A. Evans, D. Alexandrescu, Enrico Costenaro, Liang Chen

引用次数: 23

Exploiting the debug interface to support on-line test of control flow errors 利用调试接口支持控制流错误的在线测试

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604058

B. Du, M. Reorda, L. Sterpone, L. Parra, M. Portela-García, A. Lindoso, L. Entrena

引用次数: 8