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2013 IEEE 19th International On-Line Testing Symposium (IOLTS)最新文献

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Real-time checking of linear control systems using analog checksums 利用模拟校验和对线性控制系统进行实时校验
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604062
Suvadeep Banerjee, A. Banerjee, A. Chatterjee, J. Abraham
{"title":"Real-time checking of linear control systems using analog checksums","authors":"Suvadeep Banerjee, A. Banerjee, A. Chatterjee, J. Abraham","doi":"10.1109/IOLTS.2013.6604062","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604062","url":null,"abstract":"In the recent past, there has been a proliferation of complex control problems in sensor network design, multi-agent systems such as autonomous vehicles and robotics, to name a few. While prior research has focused on the design of optimal controllers for real-time systems, in the future it will become increasingly difficult to perform periodic maintenance of such systems due to their mobile and autonomous nature. Moreover, in safety-critical real-time applications it will become increasingly necessary to perform real-time monitoring of the plant as well as its controller functions for reasons of reliability and safety. In this paper, we develop, for the first time, a theory for implementing low-overhead and high coverage detection of transient errors and permanent faults in linear control systems consisting of the plant and its controller using analog checksums. The approach is demonstrated on a servo-motor control problem. It is shown that small parametric perturbations as well as transient errors are detected in real-time using the proposed checking methodology.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130835025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
When processors get old: Evaluation of BTI and HCI effects on performance and reliability 当处理器老化:BTI和HCI对性能和可靠性影响的评估
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604076
C. Sandionigi, O. Héron, C. Bertolini, R. David
{"title":"When processors get old: Evaluation of BTI and HCI effects on performance and reliability","authors":"C. Sandionigi, O. Héron, C. Bertolini, R. David","doi":"10.1109/IOLTS.2013.6604076","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604076","url":null,"abstract":"This paper investigates the problem of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on processors. We propose a performance- and reliability-aware methodology that evaluates the effects of these degradation mechanisms at design time. The performed analysis estimates the effects produced by the execution of applications, representing typical or worst case scenarios, or single instructions. As shown by the experimental results, our framework allows to estimate the performance degradation and to identify the areas of memory most subject to faults, with the objective of optimizing the system design and defining on-line strategies.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131756142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Scanning the strength of a test signal to monitor electrode degradation within bio-fluidic microsystems 扫描测试信号的强度以监测生物流体微系统中的电极退化
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604064
Qais Al-Gayem, Hong Liu, H. Khan, A. Richardson
{"title":"Scanning the strength of a test signal to monitor electrode degradation within bio-fluidic microsystems","authors":"Qais Al-Gayem, Hong Liu, H. Khan, A. Richardson","doi":"10.1109/IOLTS.2013.6604064","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604064","url":null,"abstract":"Lab-on-Chip devices are complex multifunctional heterogeneous microsystems that have the potential to strongly influence advances in important areas such as pharmacology, security, and environmental analysis. High reliability requirements in many of these microsystems are crucial which makes test more challenging especially given the need to validate multiple multi-domain interfaces and realise on-line solutions. Based on fault modeling and impedance analysis of the electrode/electrolyte interface and a customised prototype array structure, this paper proposes a self-test solution that targets degraded sensing microelectrodes within Multi Electrode Array's (MEA). The principle of this approach is to scan the strength of a test signal over the whole array to monitor the defective sensing electrodes. The test solution has been applied at the system level where an analogue multiplexer, an LCD, and a microcontroller have been used to achieve a real time condition monitoring technique.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125927289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A failure triage engine based on error trace signature extraction 基于错误跟踪签名提取的故障分类引擎
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604054
Zissis Poulos, Yu-Shen Yang, A. Veneris
{"title":"A failure triage engine based on error trace signature extraction","authors":"Zissis Poulos, Yu-Shen Yang, A. Veneris","doi":"10.1109/IOLTS.2013.6604054","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604054","url":null,"abstract":"The ever growing demand for functionally robust and error-free industrial electronics necessitates the development of techniques that will prohibit the propagation of functional errors to the final tape-out stage. This paramount requirement in the semiconductor world is imposed by the equivocal observation that functional errors slipping to silicon production introduce immense amounts of cost and jeopardize chip release dates. Functional verification and debugging are burdened with the tedious task of guaranteeing logic functionality early in the design cycle. In this paper, we present an automated method for the very first stage of functional debugging, called failure triage. Failure triage is the task of analyzing large sets of failures, grouping together those that are likely to be caused by the same design error, and then allocating those groups to the appropriate engineers for fixing. The introduced framework instruments techniques from the machine learning domain combined with the root cause analysis power of modern SAT-based debugging tools, in order to exploit information from error traces and bin the corresponding failures using clustering algorithms. Preliminary experimental results indicate an average accuracy of 93 % for the proposed failure triage engine, which corresponds to a 43 % improvement over conventional automated methods.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130550127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism FPGA上的电源故障诱发故障:对注入机理的深入分析
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604060
Loïc Zussa, J. Dutertre, J. Clédière, A. Tria
{"title":"Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism","authors":"Loïc Zussa, J. Dutertre, J. Clédière, A. Tria","doi":"10.1109/IOLTS.2013.6604060","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604060","url":null,"abstract":"Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we study the effect of negative power supply glitches on a FPGA. The obtained faults were compared to faults injected by clock glitches. As a result, both power and clock glitch induced faults were found to be identical. Because clock glitches are related to timing constraint violations, we shall consider that both power and clock glitches share this common fault injection mechanism. We also further studied the properties of this fault injection means.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114812156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Efficacy and efficiency of algorithm-based fault-tolerance on GPUs 基于算法的gpu容错效能与效率
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604090
H. Wunderlich, Claus Braun, Sebastian Halder
{"title":"Efficacy and efficiency of algorithm-based fault-tolerance on GPUs","authors":"H. Wunderlich, Claus Braun, Sebastian Halder","doi":"10.1109/IOLTS.2013.6604090","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604090","url":null,"abstract":"Computer simulations drive innovations in science and industry, and they are gaining more and more importance. However, their high computational demand generates extraordinary challenges for computing systems. Typical high-performance computing systems, which provide sufficient performance and high reliability, are extremely expensive. Modern GPUs offer high performance at very low costs, and they enable simulation applications on the desktop. However, they are increasingly prone to transient effects and other reliability threats. To fulfill the strict reliability requirements in scientific computing and simulation technology, appropriate fault tolerance measures have to be integrated into simulation applications for GPUs. Algorithm-Based Fault Tolerance on GPUs has the potential to meet these requirements. In this work we investigate the efficiency and the efficacy of ABFT for matrix operations on GPUs. We compare ABFT against fault tolerance schemes that are based on redundant computations and we evaluate its error detection capabilities.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115121375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
NBTI aging tolerance in pipeline based designs NBTI 基于管道设计的NBTI老化公差
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604047
K. Katsarou, Y. Tsiatouhas, A. Arapoyanni
{"title":"NBTI aging tolerance in pipeline based designs NBTI","authors":"K. Katsarou, Y. Tsiatouhas, A. Arapoyanni","doi":"10.1109/IOLTS.2013.6604047","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604047","url":null,"abstract":"Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Increasing fault coverage during functional test in the operational phase 在运行阶段的功能测试期间增加故障覆盖率
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604049
M. D. Carvalho, P. Bernardi, E. Sánchez, M. Reorda, O. Ballan
{"title":"Increasing fault coverage during functional test in the operational phase","authors":"M. D. Carvalho, P. Bernardi, E. Sánchez, M. Reorda, O. Ballan","doi":"10.1109/IOLTS.2013.6604049","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604049","url":null,"abstract":"A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly describe fault coverage figures to be achieved. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation exists between the system company and the device provider. However, purely functional test often shows several limitations due to the limited accessibility that it can gain on some input/output signals. This paper proposes a hybrid approach, in which a suitable hardware module is added outside a microcontroller to increase its functional testability during the operational phase. Experimental results gathered on a couple of cases-of-study are reported, showing the feasibility of the method.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"252 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes 准循环低密度奇偶校验码的高吞吐量可配置并行编码器结构
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604069
Alaa Aldin Al Hariri, F. Monteiro, L. Siéler, A. Dandache
{"title":"A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes","authors":"Alaa Aldin Al Hariri, F. Monteiro, L. Siéler, A. Dandache","doi":"10.1109/IOLTS.2013.6604069","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604069","url":null,"abstract":"In this paper, we are proposing a new architecture for fast encoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective encoder architectures. In our approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at synthesis level. High levels of parallelism can be reached, and hence high throughput achieved, due to the modular encoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through implementation on an Altera Stratix II FPGA of different encoders related to DVB-T2 and DVB-S2. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124023026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus 强化汽车应用中潜在关键系统的串行通信协议:LIN总线
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604044
A. Vaskova, M. Portela-García, M. Reorda
{"title":"Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus","authors":"A. Vaskova, M. Portela-García, M. Reorda","doi":"10.1109/IOLTS.2013.6604044","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604044","url":null,"abstract":"Serial communications protocols used in automotive systems must comply with different levels of robustness. Some subsystems in charge of n on-critical tasks are composed of cheaper and non-fault tolerant elements. As Single Event Upsets also affect these sub-systems, a complete analysis of heir robustness could highlight the critical elements and point out the possible solutions, such as selective hardening in a cost effective way. An extensive fault injection campaign has been applied to a LIN bus controller module in order to select the best mitigation techniques to harden it against soft errors. A discussion around how these mitigation techniques could affect on-line testing in the module is also presented.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115670571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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