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2013 IEEE 19th International On-Line Testing Symposium (IOLTS)最新文献

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Ef3S: An evaluation framework for flash-based systems Ef3S:基于闪存系统的评估框架
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604079
S. Carlo, Salvatore Galfano, Marco Indaco, P. Prinetto
{"title":"Ef3S: An evaluation framework for flash-based systems","authors":"S. Carlo, Salvatore Galfano, Marco Indaco, P. Prinetto","doi":"10.1109/IOLTS.2013.6604079","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604079","url":null,"abstract":"NAND Flash memories are gaining popularity in the development of electronic embedded systems for both consumer and mission-critical applications. NAND Flashes crucially influence computing systems development and performances. EF3S, a framework to easily assess NAND Flash based memory systems performances (reliability, throughput, power), is presented. The framework is based on a simulation engine and a running environment which enable developers to assess any application impact. Experimental results show functionality of the framework, analysing several performance-reliability tradeoffs of an illustrative system.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127088892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip 多核片上系统永久和临时故障下的容错自适应路由
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604043
M. Dimopoulos, Yi Gang, M. Benabdenbi, L. Anghel, N. Zergainoh, M. Nicolaidis
{"title":"Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip","authors":"M. Dimopoulos, Yi Gang, M. Benabdenbi, L. Anghel, N. Zergainoh, M. Nicolaidis","doi":"10.1109/IOLTS.2013.6604043","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604043","url":null,"abstract":"A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Integrating embedded test infrastructure in SRAM cores to detect aging 在SRAM内核中集成嵌入式测试基础设施以检测老化
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604046
W. Prates, L. Bolzani, Gurgen Harutunyan, A. Davtyan, F. Vargas, Y. Zorian
{"title":"Integrating embedded test infrastructure in SRAM cores to detect aging","authors":"W. Prates, L. Bolzani, Gurgen Harutunyan, A. Davtyan, F. Vargas, Y. Zorian","doi":"10.1109/IOLTS.2013.6604046","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604046","url":null,"abstract":"One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"258263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133137297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES A-SOFT-AES:自适应软件实现的AES容错
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604059
Fabian Oboril, Ilias Sagar, M. Tahoori
{"title":"A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES","authors":"Fabian Oboril, Ilias Sagar, M. Tahoori","doi":"10.1109/IOLTS.2013.6604059","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604059","url":null,"abstract":"The Advanced Encryption Standard (AES) is one of the most widespread encryption techniques used by millions of users worldwide. Although AES was designed to withstand linear or differential attacks, the security of encrypted messages is not guaranteed. Bit flips occurring during the encryption due to runtime failures or purposely invoked by an attacker are a major security concern and can significantly jeopardize integrity, privacy, and confidentiality and hence the security of the system. Therefore, techniques to increase the reliability (fault-tolerance) and with it the security of cryptographic systems are necessary. This work proposes a self-adaptive software-implemented fault-tolerance methodology for AES (A-SOFT-AES) to enhance its fault-tolerance. This technique is based on a pool of software-implemented fault-tolerance techniques out of which it dynamically chooses the best one in terms of performance, cost, and fault-tolerance for a wide range of fault rates. Therefore, it provides superior flexibility over classic hardware-based implementations.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130097195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Perturbation-immune radiation-hardened PLL with a switchable DMR structure 具有可切换DMR结构的抗扰抗辐射锁相环
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604063
SinNyoung Kim, A. Tsuchiya, H. Onodera
{"title":"Perturbation-immune radiation-hardened PLL with a switchable DMR structure","authors":"SinNyoung Kim, A. Tsuchiya, H. Onodera","doi":"10.1109/IOLTS.2013.6604063","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604063","url":null,"abstract":"This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is `detecting' and `switching' instead of `recovering' clock-perturbation. For robust perturbation-immunity, detecting speed is important. We identify types of clock-perturbation and - then propose a set of detectors to detect each type. With this, detectors guarantee high speed in detection.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-level synthesis for security and trust 安全和信任的高级综合
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604087
Jeyavijayan Rajendran, Huan Zhang, O. Sinanoglu, R. Karri
{"title":"High-level synthesis for security and trust","authors":"Jeyavijayan Rajendran, Huan Zhang, O. Sinanoglu, R. Karri","doi":"10.1109/IOLTS.2013.6604087","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604087","url":null,"abstract":"Trustworthiness of System-on-Chips (SoCs) is undermined by malicious logic (trojans) in third party intellectual properties (3PIPs). Concurrent Error Detection (CED) techniques can be adapted to detect malicious outputs generated by trojans. Further, by using a diverse set of 3PIP vendors and operation-to-3PIP-to-vendor allocation constraints, one can prevent collusions between 3PIPs from the same vendor. These security constraints to detect malicious outputs and to prevent collusion have been incorporated into the allocation step of high-level synthesis.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116133086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Online error detection in multiprocessor chips: A test scheduling study 多处理器芯片在线错误检测:测试调度研究
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604071
Manolis Kaliorakis, N. Foutris, D. Gizopoulos, M. Psarakis, A. Paschalis
{"title":"Online error detection in multiprocessor chips: A test scheduling study","authors":"Manolis Kaliorakis, N. Foutris, D. Gizopoulos, M. Psarakis, A. Paschalis","doi":"10.1109/IOLTS.2013.6604071","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604071","url":null,"abstract":"Multicore architectures are employed in the majority of computing domains (general-purpose microprocessors as well as specialized high-performance architectures such as network processors). Online error detection in such chips can employ effective techniques from single core microprocessors, however, effective test scheduling should be employed to minimize the overall chip test execution time which can significantly increase due to congestion on common hardware resources used by the cores. In this paper, we analyze the most important aspects of online error detection and scheduling in multiprocessor chips and evaluate test execution time in several different configurations of Intel's SCC architecture.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123908568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A fully-automated flow for ITAR-free rad-hard Atmel FPGAs 全自动化流程，适用于无itar的硬Atmel fpga
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604077
Nikolaos Andrikos, M. Violante, D. M. Codinachs
{"title":"A fully-automated flow for ITAR-free rad-hard Atmel FPGAs","authors":"Nikolaos Andrikos, M. Violante, D. M. Codinachs","doi":"10.1109/IOLTS.2013.6604077","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604077","url":null,"abstract":"In recent years, use of FPGAs has been gaining more momentum for space applications as there are cases where using them can significantly reduce developments costs and time. In order to ensure correct operation in space, they have to be rad-hard, but most of such components are subject to ITAR. Atmel is the only provider for ITAR-free rad-hard FPGAs, but the default development flow provided leaves much to be desired. The contribution of this work is two-fold: First of all, we present a fully automated flow which improves the usability of the default development flow provided by Atmel, while requiring only a bare minimum of configuration for each design. Secondly, we show how to extend this flow in order to integrate external programs which can be used as in-place substitutions of steps of the default flow. Our experiments show that the proposed flow can significantly boost both the productivity of the designers and the QoR of the final implementations.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124801559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Error resilient logic circuits under dynamic variations 动态变化下的误差弹性逻辑电路
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604094
Kwanyeob Chae, S. Mukhopadhyay
{"title":"Error resilient logic circuits under dynamic variations","authors":"Kwanyeob Chae, S. Mukhopadhyay","doi":"10.1109/IOLTS.2013.6604094","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604094","url":null,"abstract":"Summary form only given. The design of low power and robust circuits under dynamic variations has emerged as a key challenge for silicon technologies. A particularly challenging problem is to tolerate transient supply noise that can occur in nanoseconds to microseconds time scales. The use of voltage or timing safety margin helps tolerate dynamic variations but at the expense of reduced performance or increased power dissipation. This talk will present adaptive circuit techniques to design resilient pipelines under fast transient variations. The presented techniques will allow a pipeline circuit to operate with minimal safety margin while preventing timing errors by adaptive clocking as well as time-borrowing and clock stretching. The measurement data from test-chips designed in 130nm CMOS technology will be presented to demonstrate the effectiveness of adaptive circuit techniques in designing low-power and resilient pipeline circuits.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130307307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
At-speed BIST for interposer wires supporting on-the-spot diagnosis 用于支持现场诊断的中间线的高速BIST
2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604053
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
{"title":"At-speed BIST for interposer wires supporting on-the-spot diagnosis","authors":"Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng","doi":"10.1109/IOLTS.2013.6604053","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604053","url":null,"abstract":"Testing the speed of post-bond interposer wires in a 2.5-D stacked IC is essential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate through the interposer wire and reach the other end, then the interposer wire is considered fault-free. Otherwise, it indicates the presence of a delay fault. This new test technique has several technical merits. For example, the Design-for-Testability (DfT) circuit for an interposer wire is similar to the boundary scan cell and can be controlled through scan chain. Also, it can be easily adapted to perform at-speed Built-In Self-Test (BIST) supporting on-the-spot diagnosis.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129193964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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