2013 IEEE 19th International On-Line Testing Symposium (IOLTS)最新文献_第2页

Challenges of RF and mixed signal design under process variability 工艺变异性下射频和混合信号设计的挑战

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604095

G. Panagopoulos, P. Riess, P. Baumgartner

引用次数: 0

Exploiting application resiliency for energy-efficient and adequately-reliable operation 利用应用程序弹性实现节能和足够可靠的操作

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604093

G. Karakonstantis, David Atienza Alonso, Andy Burg

{"title":"Exploiting application resiliency for energy-efficient and adequately-reliable operation","authors":"G. Karakonstantis, David Atienza Alonso, Andy Burg","doi":"10.1109/IOLTS.2013.6604093","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604093","url":null,"abstract":"Summary form only given. Currently, manufacturers go to great lengths for mitigating the effects of parametric variations and scaled supply voltages by adopting conservative layout rules and by introducing several mechanisms providing redundancy on various layers of design abstraction. Such measures may have accomplished to hide any inaccurate behavior of nanometer circuits from the application layers and maintain acceptable yield levels, but unfortunately the large energy, performance, and area overheads that they incur limit their viability, especially as we move beyond the 45nm node. Such a reality has urged us to rethink the current design flows and question if such considerable overhead is really required given that many modern signal-processing workloads such as in multimedia, communications, or biomedical systems are inherently complexity/energy-scalable and can even tolerate a degree of imprecision in their computations and stored data. By taking advantage of this inherent resilience of many applications and trading off output precision and quality of service we could reduce energy usage and reliability costs, since by allowing some computations to be approximate we can alleviate the burden of correctness overhead imposed by the traditional design paradigm. In this paper, we discuss methods that could reveal and exploit the resilience and certain characteristics of biomedical and communication applications for achieving adequately-reliable and energy efficient operation, while limiting or even avoiding the penalties required by traditional approaches.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121086181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accelerating post silicon debug of deep electrical faults 加速深度电气故障的硅后调试

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604052

Bao Le, D. Sengupta, A. Veneris, Zissis Poulos

引用次数: 2

Evaluating a low cost robustness improvement in SRAM-based FPGAs 评估基于sram的fpga的低成本鲁棒性改进

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604072

M. Jrad, R. Leveugle

引用次数: 1

State-aware single event analysis for sequential logic 序列逻辑的状态感知单事件分析

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604067

D. Alexandrescu, Enrico Costenaro, A. Evans

引用次数: 10

On-line testing for differential fault attacks in cryptographic circuits 密码电路差分故障攻击的在线测试

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604084

Debdeep Mukhopadhyay

{"title":"On-line testing for differential fault attacks in cryptographic circuits","authors":"Debdeep Mukhopadhyay","doi":"10.1109/IOLTS.2013.6604084","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604084","url":null,"abstract":"Faults have been found to be catastrophic for the security of ciphers. Random faults inside a cipher implementation, trigger intentionally or accidentally, can be shown to reduce the key space of ciphers drastically. Even world-wide standard ciphers, like the Advanced Encryption Standard (AES) can be shown to be cryptanalyzed when the faulty ciphertexts are exposed to the outside world. Our recent findings show that fluctuations of the operating conditions of a circuit introduces circuit marginalities, which are manifested as exploitable multiple byte faults. The paper subsequently deals with a natural follow up question, how to test these faults? Can we adopt classical fault tolerance methods to detect these malicious faults? We show that while classical fault tolerance assumes uniform distribution of faults, the fault attacker introduces biased faults. On the other hand, while classical fault tolerance attempts to target all faults, most of the attacks exploit a small subspace of the entire fault space. This hiatus implies the necessity of the emergence of novel on-line methodologies for fault detection. The paper concludes with the requirement of proofs for 100% fault coverage of the attack-exploitable space, vs the simulation based approaches of classical fault tolerance.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A smart test controller for scan chains in secure circuits 安全电路中扫描链的智能测试控制器

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604085

Jean DaRolt, G. D. Natale, M. Flottes, B. Rouzeyre

引用次数: 25

Measuring the performance impact of permanent faults in modern microprocessor architectures 现代微处理器体系结构中永久性故障对性能影响的测量

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604075

N. Foutris, D. Gizopoulos, J. Kalamatianos, Vilas Sridharan

{"title":"Measuring the performance impact of permanent faults in modern microprocessor architectures","authors":"N. Foutris, D. Gizopoulos, J. Kalamatianos, Vilas Sridharan","doi":"10.1109/IOLTS.2013.6604075","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604075","url":null,"abstract":"Large silicon parts of modern microprocessors are dedicated to components that increase performance but don't determine functional correctness. Permanent hardware faults in such components lead to performance fluctuation (not necessarily degradation) but do not produce functional errors. This fact has been identified previously but neither an accurate classification of the behavior of permanent faults in these components over a set of CPU benchmarks nor detailed measurements of the magnitude of their performance impact has been reported. Depending on such measurements the performance-related components of microprocessors can be disabled in fine or coarse granularities, salvaging the microprocessor functionality although at different performance levels. In this paper, we describe a comprehensive framework for the analysis of the impact of permanent faults in the arrays and the control logic of key performance components. We apply a statistically safe, fault injection campaign to the performance components on a modified version of the cycle accurate x86-based architectural simulator PTLsim running the SPEC2006 benchmarks suite. Our evaluation reveals the differences in the effect of faults and their performance impact across the components as well as within each component. We summarize the fault effect classification and further analyze the performance impact (IPC) of faults in their arrays and control parts.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114530338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery 利用声波探测器进行错误恢复，降低缓存的DUE-FIT

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604056

Gaurang Upasani, X. Vera, Antonio González

引用次数: 12

Parity check for m-of-n delay insensitive codes m (n)延迟不敏感码的奇偶校验

2013 IEEE 19th International On-Line Testing Symposium (IOLTS) Pub Date : 2013-07-08 DOI: 10.1109/IOLTS.2013.6604068

Julian J. H. Pontes, Ney Laert Vilar Calazans, P. Vivet

引用次数: 3