2013 IEEE 19th International On-Line Testing Symposium (IOLTS)最新文献

{"title":"Error-tolerance evaluation and design techniques for motion estimation computing arrays","authors":"Shyue-Kung Lu, Ming-Chang Chen, Yen-Chi Chen","doi":"10.1109/IOLTS.2013.6604070","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604070","url":null,"abstract":"In this paper, we propose evaluation flow for estimating the performance degradation of motion estimation (ME) architectures when faults occur and decide their acceptability. Moreover, when a fault is evaluated as unacceptable, a swap-based error-tolerance (ET) technique is proposed to increase the acceptability of this fault. According to experimental results, the acceptability and effective yield can be improved significantly with negligible hardware overhead.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117203417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations","authors":"G. Tsiligiannis, E. Vatajelu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel, F. Wrobel, F. Saigné","doi":"10.1109/IOLTS.2013.6604066","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604066","url":null,"abstract":"In current technologies, the robustness of Static Random Access Memories (SRAM) has to be investigated under any possible source of disturbance. In this paper, we evaluate the reliability of an SRAM cell exposed to atmospheric neutron radiation, affected by random threshold voltage variation and under different operation conditions (supply voltage, process corner and temperature). The SRAM cell's Soft Error Rate (SER) at simulation level is estimated using accurate models of atmospheric neutron induced currents. The study shows that in extreme operation conditions and under random process variability, the SER of an SRAM can reach values up to 3X larger than the nominal value, or down to 2X smaller than the nominal value. This large SER range confirms the importance of our study and justifies the need for further evaluation of circuits under radiation at the simulation level.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"53 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120907714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigating the limits of AVF analysis in the presence of multiple bit errors","authors":"M. Maniatakos, M. Michael, Y. Makris","doi":"10.1109/IOLTS.2013.6604050","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604050","url":null,"abstract":"We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up to 55% of such strikes result in Multiple Bit Upsets (MBUs). Consequently, the accuracy of popular vulnerability analysis methods, such as the Architecural Vulnerability Factor (AVF) and Failures In Time (FIT) rate estimates based on the SBF assumption comes into question, especially in modern microprocessors which contain a significant amount of memory elements. Towards alleviating this concern, we present an extensive infrastructure which enables MBU vulnerability analysis in modern microprocessors. Using this infrastructure and a modern microprocessor model, we perform a large scale MBU vulnerability analysis study and we report two key findings: (i) the SBF fault model overestimates vulnerability by up to 71%, as compared to a more realistic modeling and distribution of faults in the 90nm and 65nm processes, and (ii) the rank-ordered lists of critical bits, as computed through the SBF and MBU models, respectively, are very similar, as indicated by the average rank difference of a bit which is less than 1.45%.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125125003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors","authors":"O. Ballan, P. Bernardi, B. Yazdani, E. Sánchez","doi":"10.1109/IOLTS.2013.6604055","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604055","url":null,"abstract":"Nowadays, Software-Based Self-Test (SBST) is growing in importance especially in the on-line test scenario for safety critical systems such as automotive. This paper concentrates on the coverage by SBST of those faults in the scan chain that can impact the behavior of the embedded processor while working in its application field. A technique is described that is able to systematically tackle these faults after a scan chain analysis. Results are demonstrating the effectiveness and showing the costs of the proposed approach on a 32-bit embedded processor included in an industrial System-on-Chip used in the automotive field.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Increasing the robustness of CUDA Fermi GPU-based systems","authors":"S. Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/IOLTS.2013.6604088","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604088","url":null,"abstract":"Nowadays Graphical processing Units (GPUs) have become increasingly popular due to their high computational power and low prices. This makes them particularly suitable for high-performance computing applications, like data elaboration and image processing. In these fields, the capability of properly work even in presence of faults is mandatory. This paper presents an innovative approach, that combines a Software Based Self Test & Diagnosis (SBSTD) methodology with a fault mitigation strategy, to increase the robustness of a CUDA Fermi GPU-based system.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122976942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental evaluation of GPUs radiation sensitivity and algorithm-based fault tolerance efficiency","authors":"P. Rech, L. Carro","doi":"10.1109/IOLTS.2013.6604091","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604091","url":null,"abstract":"Experimental results demonstrate that Graphic Processing Units are very prone to be corrupted by neutrons. We have performed several experimental campaigns at ISIS, UK and at LANSCE, Los Alamos, NM, USA accessing the sensitivity of the GPU internal resources as well as the error rate of common parallel algorithms. Experiments highlight output error patterns and radiation responses that can be fruitfully used to design optimized Algorithm-Based Fault Tolerance strategies and provide pragmatic programming guidelines to increase the code reliability with low computational overhead.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transparent BIST for ECC-based memory repair","authors":"M. Nicolaidis, P. Papavramidou","doi":"10.1109/IOLTS.2013.6604082","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604082","url":null,"abstract":"Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly-reliable integer matrix multiplication via numerical packing","authors":"Ijeoma Anarado, M. A. Anam, D. Anastasia, F. Verdicchio, Y. Andreopoulos","doi":"10.1109/IOLTS.2013.6604045","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604045","url":null,"abstract":"The generic matrix multiply (GEMM) routine comprises the compute and memory-intensive part of many information retrieval, relevance ranking and object recognition systems. Because of the prevalence of GEMM in these applications, ensuring its robustness to transient hardware faults is of paramount importance for highly-efficientlhighly-reliable systems. This is currently accomplished via error control coding (ECC) or via dual modular redundancy (DMR) approaches that produce a separate set of “parity” results to allow for fault detection in GEMM. We introduce a third family of methods for fault detection in integer matrix products based on the concept of numerical packing. The key difference of the new approach against ECC and DMR approaches is the production of redundant results within the numerical representation of the inputs rather than as a separate set of parity results. In this way, high reliability is ensured within integer matrix products while allowing for: (i) in-place storage; (ii) usage of any off-the-shelf 64-bit floating-point GEMM routine; (iii) computational overhead that is independent of the GEMM inner dimension. The only detriment against a conventional (i.e. fault-intolerant) integer matrix multiplication based on 32-bit floating-point GEMM is the sacrifice of approximately 30.6% of the bitwidth of the numerical representation. However, unlike ECC methods that can reliably detect only up to a few faults per GEMM computation (typically two), the proposed method attains more than “12 nines” reliability, i.e. it will only fail to detect 1 fault out of more than 1 trillion arbitrary faults in the GEMM operations. As such, it achieves reliability that approaches that of DMR, at a very small fraction of its cost. Specifically, a single-threaded software realization of our proposal on an Intel i7-3632QM 2.2GHz processor (Ivy Bridge architecture with AVX support) incurs, on average, only 19% increase of execution time against an optimized, fault-intolerant, 32-bit GEMM routine over a range of matrix sizes and it remains more than 80% more efficient than a DMR-based GEMM.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115484507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded high-precision frequency-based capacitor measurement system","authors":"L. Welter, P. Dreux, J. Portal, H. Aziza","doi":"10.1109/IOLTS.2013.6604061","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604061","url":null,"abstract":"This paper presents a direct way to measure the electrical value of capacitors embedded in a circuit using a ring-oscillator. A calibration system ensures robustness towards temperature, power supply and process variations. The measurement is largely automated to minimize the use of external instrumentation and to speed-up the measurement process while giving a digital signature of the capacitor value. Design-Of-Experiment (DOE) methodology has been conducted in order to validate the ability of the system to measure robustly a large range of small capacitors.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115888425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Timing vulnerability factors of sequential elements in modern microprocessors","authors":"A. Bramnik, Andrei Sherban, N. Seifert","doi":"10.1109/IOLTS.2013.6604051","DOIUrl":"https://doi.org/10.1109/IOLTS.2013.6604051","url":null,"abstract":"An efficient and novel technique for computing timing vulnerability factors (TVF) in modern complex synchronous designs is introduced, where all key inputs are based on static timing data readily available in most design databases. The benefits of TVF for modern microprocessors and strategies to reduce TVF, and hence the overall soft error rate (SER), are presented.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117072195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}