Integrating embedded test infrastructure in SRAM cores to detect aging

Abstract

One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion.