2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献_第6页

Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS 完全集成的开关电容电压调节器，具有片上电流传感和32nm SOI CMOS工作负载优化

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273504

Xiaoyang Mi, Debashis Mandal, V. Sathe, B. Bakkaloglu, Jae-sun Seo

{"title":"Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS","authors":"Xiaoyang Mi, Debashis Mandal, V. Sathe, B. Bakkaloglu, Jae-sun Seo","doi":"10.1109/ISLPED.2015.7273504","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273504","url":null,"abstract":"Efficient, stable, and fast power delivery against fluctuating workloads have become a critical concern for applications from battery-powered devices to high-performance servers. With high density on-chip capacitors, fully-integrated switched-capacitor (SC) voltage converters provide high efficiency down-conversion from a battery or off-chip voltage regulation modules. However, maintaining such efficiency with minimal supply noise across a wide range of fluctuating load currents remains challenging. In this paper, we propose an on-chip current sensing technique to dynamically modulate both switching frequency and switch widths of SC voltage converters, enhancing fast transient response and higher efficiency across a wide range of load currents. In conjunction with SC converters, we employ a low-dropout regulator (LDO) driven by a push-pull operational transconductance amplifier (OTA), whose current is mirrored and sensed with minimal power and efficiency overhead. The sensed load current directly controls the frequency and width of SC converters through a voltage-controlled oscillator (VCO) and a time-to-digital converter, respectively. In 32nm SOI CMOS, the proposed voltage regulator maintains 77-82% efficiency at 0.95V output voltage with less than 20mV steady-state ripple across 10X load current range of 100mA-1A and 33mV droop voltage for a 80mA/ns load transition, while providing a projected current density of 6W/mm2.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116625737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A novel slope detection technique for robust STTRAM sensing 一种鲁棒stream传感斜坡检测新技术

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273482

Seyedhamidreza Motaman, Swaroop Ghosh, J. Kulkarni

引用次数: 22

A micropower energy harvesting circuit with piezoelectric transformer-based ultra-low voltage start-up 一种基于压电变压器的超低电压启动微功率能量收集电路

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273527

A. Romani, Antonio Camarda, A. Baldazzi, M. Tartagni

引用次数: 10

Power benefit study of monolithic 3D IC at the 7nm technology node 7nm工艺节点单片3D集成电路的功耗效益研究

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273514

Kyungwook Chang, Kartik Acharya, S. Sinha, B. Cline, G. Yeric, S. Lim

{"title":"Power benefit study of monolithic 3D IC at the 7nm technology node","authors":"Kyungwook Chang, Kartik Acharya, S. Sinha, B. Cline, G. Yeric, S. Lim","doi":"10.1109/ISLPED.2015.7273514","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273514","url":null,"abstract":"Monolithic 3D IC (M3D) is one potential technology to help with the challenges of continued circuit power and performance scaling. In this paper, for the first time, the power benefits of monolithic 3D IC (M3D) using a 7nm FinFET technology are investigated. The predictive 7nm Process Design Kit (PDK) and standard cell library for both high performance (HP) and low standby power (LSTP) device technologies are built based on NanGate 45nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. In addition, we implement full-chip M3D GDS layouts using both 7nm HP and LSTP cells and industry-standard physical design tools, and evaluate the resulting full-chip power, performance, and area metrics. Our study first shows that 7nm HP M3D designs outperform 7nm HP 2D designs by 16.8% in terms of iso-performance total power reduction. Moreover, 7nm LSTP M3D designs reduce the total power consumption by 14.3% compared to their 2D counterparts. This convincingly demonstrates the power benefits of M3D technologies in both high performance as well as low power future generation devices.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126584589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems 一种用于深层脑传感和刺激系统的神经形态神经尖峰聚类处理器

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273496

Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok

引用次数: 14

Fine-grained write scheduling for PCM performance improvement under write power budget 在写功率预算下，用于改进PCM性能的细粒度写调度

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273484

Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li

{"title":"Fine-grained write scheduling for PCM performance improvement under write power budget","authors":"Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li","doi":"10.1109/ISLPED.2015.7273484","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273484","url":null,"abstract":"Phase-change memory (PCM) has gained much attention recently since it offers several advantages over DRAM, such as high cell density and low leakage power. PCM has similar read power and latency as DRAM; however, its write power and latency are significantly higher than DRAM. Therefore, one challenge with PCM is how to increase write throughput under write power budget constraints. To increase write concurrency, PCM often adopts division programming, where a write occurs in a series of divisions, so that writes to different banks proceed concurrently. In this study, we observe that since the write scheduling granularity in the memory controller differs from the actual write granularity in PCM chips, i.e., requests vs. divisions, the available power budget cannot be fully utilized. We therefore propose enhancing the interface between the memory controller and PCM chips to allow the memory controller to schedule writes in the division granularity. To further increase power budget utilization, we design a variable-length division mechanism to allow the division granularity to be adjusted at runtime according to the available write power budget. Our experimental results show that these techniques improve system performance by up to 65%.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125676182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Lucid infrared thermography of thermally-constrained processors 热约束处理器的清晰红外热成像

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273538

H. Amrouch, J. Henkel

{"title":"Lucid infrared thermography of thermally-constrained processors","authors":"H. Amrouch, J. Henkel","doi":"10.1109/ISLPED.2015.7273538","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273538","url":null,"abstract":"Thermal analysis is a prerequisite for developing reliability increasing techniques for thermally-constrained processors, i.e. processors with a high power density. For that purpose, infrared (IR) camera measurement setups have been deployed with the purpose to provide direct feedback of the impact that thermal mitigation techniques have. To obtain lucid IR images1, the IR-opaque cooling must be removed and hence, an alternative IR-transparent cooling needs to be provided to protect the chip. To this end, the majority of state-of-the-art employs an IR coolant liquid to prevent the chip from overheating. The problem is that several aspects like thermal convection may interfere with the measured IR radiations resulting in equivocal IR images. Thus, they decrease the accuracy in a way that leads to incorrectly estimating reliability. Solving this prominent problem, we introduce an IR-transparent cooling that cools the chip from its rear side allowing the camera to perspicuously capture the IR emissions as no additional layer in between impedes the radiation. It maintains the on-chip temperatures within a safe range equivalent to the original heat sink-based cooling. We demonstrate how state-of-the-art inaccurate thermal analysis results in incorrectly estimating reliability. Our setup is the most accurate, least intrusive one that has been both proposed and actually applied to state-of-the-art multi-cores (Intel 45nm dual-core and 22nm octa-core).","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

ThermTap: An online power analyzer and thermal simulator for Android devices ThermTap:用于Android设备的在线功率分析仪和热模拟器

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273537

M. Dousti, Majid Ghasemi-Gol, M. Nazemi, M. Pedram

引用次数: 18

Analysis and optimization of CMOS switched-capacitor converters CMOS开关电容变换器的分析与优化

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273535

V. Sathe, Jae-sun Seo

引用次数: 5

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits 鲁棒组合电路的协同门实现选择与自适应分配

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273501

Hao He, Jiafan Wang, Jiang Hu

引用次数: 2