2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献_第5页

Post placement leakage reduction with stress-enhanced filler cells 后放置泄漏减少应力增强填充电池

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273531

J. Choy, V. Sukharev, A. Kteyan, Henrik Hovsepyan, R. Venkatraman, R. Castagnetti

引用次数: 0

Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup 通过早期标签查找减少集合关联L1指令缓存的动态能量

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273489

Wei Zhang, Hang Zhang, J. Lach

引用次数: 2

Adaptive sprinting: How to get the most out of Phase Change based passive cooling 自适应冲刺:如何充分利用基于相变的被动冷却

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273487

Fulya Kaplan, A. Coskun

{"title":"Adaptive sprinting: How to get the most out of Phase Change based passive cooling","authors":"Fulya Kaplan, A. Coskun","doi":"10.1109/ISLPED.2015.7273487","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273487","url":null,"abstract":"CMOS scaling trends lead to elevated on-chip temperatures, which substantially limit the performance of today's processors. To improve thermal efficiency, Phase Change Materials (PCMs) have recently been used as passive cooling solutions. PCMs store large amount of heat at near-constant temperature during phase change, allowing strategies such as computational sprinting. While existing sprinting methods allow short performance boosts, there is significant unexplored potential in improving performance on systems with PCM-enhanced cooling. To this end, this paper proposes a novel runtime management policy driven by observations that are not captured by prior techniques: (i) PCM melts non-uniformly due to spatially heterogeneous on-chip heat distribution; (ii) power consumption during sprinting is highly application dependent and assuming a fixed sprinting power leads to lower thermal efficiency; (iii) if we monitor the remaining PCM energy at various locations, we can utilize the PCM heat storage capability much more efficiently. The proposed Adaptive Sprinting policy exploits these observations to extend sprinting duration for increased performance gains. Our policy monitors the remaining PCM energy corresponding to each core at runtime, and using this information, it decides on the number, the location and the voltage-frequency (V/f) setting of the sprinting cores. Experimental evaluation including a detailed phase change thermal model demonstrates 29% performance improvement, 22% energy savings, and 43% energy delay product (EDP) reduction on average, compared to prior strategies.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116628223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures 多核架构中热缓解技术快速原型设计和评估的仿真框架

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273485

Tanguy Sassolas, C. Sandionigi, Alexandre Guerre, Julien Mottin, P. Vivet, H. Boussetta, N. Peltier

引用次数: 2

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory 高带宽自旋传递转矩随机存取存储器参考电路分析

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273541

Byungkyu Song, T. Na, Seong-ook Jung, Jung Pill Kim, Seung H. Kang

引用次数: 4

Design and optimization of a reconfigurable power delivery network for large-area, DVS-enabled OLED displays 设计和优化用于大面积、支持dvs的OLED显示器的可重构电源传输网络

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273507

Woojoo Lee, Yanzhi Wang, Donghwa Shin, Shahin Nazarian, Massoud Pedram

{"title":"Design and optimization of a reconfigurable power delivery network for large-area, DVS-enabled OLED displays","authors":"Woojoo Lee, Yanzhi Wang, Donghwa Shin, Shahin Nazarian, Massoud Pedram","doi":"10.1109/ISLPED.2015.7273507","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273507","url":null,"abstract":"Dynamic voltage scaling (DVS) has proven effective in minimizing the power consumption of OLED displays, resulting only in minimal image distortion. This technique has been extended to perform zone-specific DVS by dividing the panel area into zones and applying independent DVS to each zone based on the displayed content. The application of the latter technique to large-area OLED displays has not been done in part due to a high overhead of its dedicated DC-DC converter for each zone and low conversion efficiency when the load current of each converter lies outside the desirable range. To address this issue, this work proposes a reconfigurable power delivery network architecture, comprised of a small number of DC-DC converters, a switch network and an online controller, to realize fine-grained (zone-specific) DVS in large-area OLED display panels. The proposed framework consistently achieves high power conversion efficiency and significant energy saving while preserving the image quality. Experimental results demonstrate that up to 36% power savings can be achieved in a 65\" 4K Ultra high-definition OLED display by using the proposed framework.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122739938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach 暗硅时代多核平台的动态电源管理:多目标控制方法

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273517

A. Rahmani, M. Haghbayan, A. Kanduri, Awet Yemane Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, H. Tenhunen

{"title":"Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach","authors":"A. Rahmani, M. Haghbayan, A. Kanduri, Awet Yemane Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, H. Tenhunen","doi":"10.1109/ISLPED.2015.7273517","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273517","url":null,"abstract":"Power management of NoC-based many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129344104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

High-efficiency crossbar switches using capacitively coupled signaling 使用电容耦合信号的高效交叉开关

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273497

Cagla Cakir, R. Ho, J. Lexau, K. Mai

{"title":"High-efficiency crossbar switches using capacitively coupled signaling","authors":"Cagla Cakir, R. Ho, J. Lexau, K. Mai","doi":"10.1109/ISLPED.2015.7273497","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273497","url":null,"abstract":"As process technologies have scaled, the increasing number of processor cores and memories on a single die has also driven the need for more complex on-chip interconnection networks. Crossbar switches are primary building blocks in such networks-on-chip, as they can be used as fast single-stage networks or as the core of the router switch in multi-stage networks. While crossbars offer non-blocking, single-hop, all-to-all communication, they tend to scale poorly with the number of nodes due to the latency and energy of the long wires and high-radix multiplexor structures needed. To combat these limitations, we propose a low-swing crossbar design that uses capacitively driven wires and capacitively coupled multiplexers. Capacitively driven wires offer low swing signaling, higher bandwidths, and low energy consumption, while capacitively coupled multiplexers offer reduced parasitic loading from the inactive inputs. We present a 16×16 64b low-swing crossbar switch designed in a TSMC 40nm CMOS bulk process. Post-layout simulation shows it operating at a maximum frequency of 2.2GHz, achieving a bandwidth of 2.56Tb/s at 0.9V (nominal Vdd) with an area of 0.94mm2. Total energy consumption for full, half, and minimum bandwidths are 110pJ, 84pJ, and 64pJ respectively, thus offering an efficiency of 10.49 Tbps/W, a 3X improvement over previously published results.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"78 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133605077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones 运行时功耗优化的软硬件交互:多核智能手机上嵌入式Linux的案例研究

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273508

Anup Das, M. J. Walker, Andreas Hansson, B. Al-Hashimi, G. Merrett

{"title":"Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones","authors":"Anup Das, M. J. Walker, Andreas Hansson, B. Al-Hashimi, G. Merrett","doi":"10.1109/ISLPED.2015.7273508","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273508","url":null,"abstract":"Applications running on smartphones interact with the hardware and the system software differently, resulting in widely varying power consumption and hence thermal profiles. Typically, these smartphone platforms expose some hardware power control features to users, controlled through software governors such as cpufreq for dynamic voltage-frequency scaling (DVFS) and cpuquiet for dynamic core selection (DCS). Operating systems on these platforms manage these governors conservatively, independent of application's performance requirement. To address this, we propose an alternative approach, which uses reinforcement learning to explore the trade-off between power saving opportunities using DVFS and DCS and application's performance at run-time. The objective is to reduce power consumption, taking into consideration dynamic power, leakage power, and the inter-dependency between temperature and power. The reinforcement learning-based control is validated as a case-study on ARM A15-based nvidia's tegra smartphone through its implementation as a run-time manager (RTM). This RTM interfaces with different hardware performance counters and the embedded Linux Operating System through (1) the cpuquiet API to select cores at run-time; and (2) the cpufreq API to scale the frequency of active cores. Experiments with mobile and high performance applications demonstrate that the proposed approach achieves an average 22% (7-40%) power reduction compared to existing techniques.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131951857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators 利用集成的低掉差调节器探索资源受限加密引擎的功率攻击保护

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273503

Arvind Singh, Monodeep Kar, J. Ko, S. Mukhopadhyay

引用次数: 25