2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献

Fixing sensor-related energy bugs through automated sensing policy instrumentation 通过自动传感策略仪表修复传感器相关的能量bug

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273534

Yuanchun Li, Yao Guo, Junjun Kong, Xiangqun Chen

引用次数: 7

Energy stealing - an exploration into unperceived activities on mobile systems 能量窃取-探索移动系统上未被察觉的活动

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273524

Chi-Hsuan Lin, Yu-Ming Chang, P. Hsiu, Yuan-Hao Chang

引用次数: 3

DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing DVAS:动态电压精度缩放提高能源效率的近似计算

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273520

Bert Moons, M. Verhelst

{"title":"DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing","authors":"Bert Moons, M. Verhelst","doi":"10.1109/ISLPED.2015.7273520","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273520","url":null,"abstract":"A wide variety of existing and emerging applications in recognition, mining and synthesis and machine-to-human interactions tolerate small errors or deviations in their computational results. Digital systems can exploit this error tolerance to increase their energy efficiency, which is crucial in high performance wearable electronics and in emerging low power systems for the internet-of-things. A dynamic energy-accuracy trade-off brings an extra degree of freedom for system level power management. We introduce the concept of Dynamic Voltage Accuracy Scaling and illustrate its analogy to Dynamic Voltage Frequency Scaling. Dynamic Voltage Accuracy Scaling proves to have higher energy gains at most output qualities compared to other approximate computing alternatives. This work further generalizes the Dynamic Voltage Accuracy Scaling concept to pipelined structures and quantifies its energy overhead. Shallow pipelined multipliers with two to four dynamic accuracy modes can be supported with limited (<; 10-20%) overhead, resulting in significant energy savings of up to 90% or more for less than 2% mean error. DVAS is finally applied to a JPEG image processing application, demonstrating large system level gains without noticeable impact to user or application.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128492508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

A win-win camera: Quality-enhanced power-saving images on mobile OLED displays 一个双赢的相机:移动OLED显示屏上的高质量节能图像

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273525

Chih-Kai Kang, Chun-Han Lin, P. Hsiu

引用次数: 14

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs 混合近似乘法器架构改善功率精度的权衡

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273494

Georgios Zervakis, S. Xydis, Kostas Tsoumanis, D. Soudris, K. Pekmestzi

{"title":"Hybrid approximate multiplier architectures for improved power-accuracy trade-offs","authors":"Georgios Zervakis, S. Xydis, Kostas Tsoumanis, D. Soudris, K. Pekmestzi","doi":"10.1109/ISLPED.2015.7273494","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273494","url":null,"abstract":"Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129142462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Design of fine-grained sequential approximate circuits using probability-aware fault emulation 基于概率感知故障仿真的细粒度序列近似电路设计

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273493

D. May, W. Stechele

{"title":"Design of fine-grained sequential approximate circuits using probability-aware fault emulation","authors":"D. May, W. Stechele","doi":"10.1109/ISLPED.2015.7273493","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273493","url":null,"abstract":"Approximate Computing has recently drawn interest due to its promise to substantially decrease the power consumption of integrated circuits. By tolerating a certain imprecision at a circuit output, the circuit can be operated at a more resource-saving state. For instance, parts of the circuit could be switched off or driven at sub-threshold voltage. Clearly, not all applications are suitable for this approach. Especially applications from the signal and image processing domain are applicable, due to their intrinsic tolerance to imprecision. But even for these circuits, one has to be very careful where to approximate a circuit and to what extent, in order not to fall below a minimum required QoS. In this paper we are presenting an approach to generate approximate circuits from existing deterministic implementations. The flow reaches from application-driven QoS definition down to approximated RTL. We are employing FPGA-based fault emulation of the circuit in order to find out how faults, i.e. imprecisions in the circuit, affect the overall circuit behavior. Most existing approaches only consider combinational circuits. Our proposed methodology is able to approximate complete sequential circuits. Due to the FPGA-based emulation, our approach is very fast and accurate. And furthermore, it allows us to fine-granular tune the resulting precision to the required QoS, in order to get the most out of the approximation.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123454652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Power management in the Intel Xeon E5 v3 Intel至强E5 v3的电源管理

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273542

A. Varma, W. Bowhill, Jason Crop, Corey Gough, B. Griffith, Dan Kingsley, K. Sistla

{"title":"Power management in the Intel Xeon E5 v3","authors":"A. Varma, W. Bowhill, Jason Crop, Corey Gough, B. Griffith, Dan Kingsley, K. Sistla","doi":"10.1109/ISLPED.2015.7273542","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273542","url":null,"abstract":"The Intel Xeon E5 v3 family is the latest generation of enterprise-grade, high-performance, Xeon microprocessors. It implements several new power-management technologies and features aimed at improving power/performance efficiency, increasing performance, and improving power delivery. It is the first commercial x86 processor to manage voltage/frequency optimizations on a per-core granularity. This is done by combining a) fine-grained on-die per-core voltage regulators, enabling every core on the processor to run at a different voltage, b) per-core clock management, enabling each core to run at a different frequency, and c) advanced power management algorithms for optimizing the frequency and voltage of each core based on OS requests, system utilization, on-die sensors, and silicon characteristics. The Xeon E5 v3 family also introduces a new maximum-power-draw (Pmax) management approach. This paper describes some of the technical challenges, solutions, and lessons learned during the architecture, design, and productization of this new generation of microprocessor architecture, as well as the power/performance improvements measured for server workloads.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130205833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Low-power detection of sternocleidomastoid muscle contraction for asthma assessment and control 低倍率检测胸锁乳突肌收缩对哮喘的评估和控制

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273511

Jun Luan, Seung Jae Lee, P. Chou

引用次数: 3

Experimental characterization of in-package microfluidic cooling on a System-on-Chip 片上系统封装微流控冷却的实验表征

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273488

W. Yueh, Z. Wan, Y. Joshi, S. Mukhopadhyay

引用次数: 1

Battery-aware energy-optimal Electric Vehicle driving management 电池感知能量优化的电动汽车驾驶管理

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273539

K. Vatanparvar, Jiang Wan, M. A. Faruque

引用次数: 30