2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)最新文献_第2页

Hierarchical power budgeting for Dark Silicon chips 暗硅芯片的分层功率预算

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273516

M. U. Khan, M. Shafique, J. Henkel

引用次数: 11

Enabling energy efficient Hybrid Memory Cube systems with erasure codes 启用具有擦除码的节能混合记忆体系统

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273492

Shibo Wang, Yanwei Song, M. N. Bojnordi, Engin Ipek

引用次数: 5

An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect 具有表面波调制器和互连的高能效低串扰CMOS亚太赫兹I/O

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273499

Yuan Liang, Hao Yu, Junfeng Zhao, Wei Yang, Yuangang Wang

{"title":"An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect","authors":"Yuan Liang, Hao Yu, Junfeng Zhao, Wei Yang, Yuangang Wang","doi":"10.1109/ISLPED.2015.7273499","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273499","url":null,"abstract":"Free-space EM-wave based GHz interconnect has significant loss and crosstalk that cannot be deployed as low-power and dense I/Os for future network-on-chip (NoC) integration of many-core and memory. This paper proposes an energy-efficient and low-crosstalk sub-THz (0.1T-1T) I/O with use of surface-wave based modulator and interconnects in CMOS. By introducing sub-wavelength periodical corrugation structure onto transmission line, the surface-wave is established to propagate signal that is strongly localized on surface of top-layer metal wire, which results in low coupling into lossy substrate and neighboring metal wires. As such, significant power saving and cross-talk reduction can be observed with high communication bandwidth. In addition, a high on/off-ratio surface-wave modulator is also proposed to support on-chip THz communication. As designed in 65nm CMOS, the results have shown that the proposed surface-wave I/O interface achieves 25Gbps data rate and 0.016pJ/bit/mm energy efficiency at 140GHz carrier frequency over 20mm surface-wave channels. They can be placed with 2.4μm channel spacing and a -20dB crosstalk ratio. The surface-wave modulator also achieves significant reduction of radiation loss with 23dB extinction ratio.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133319373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Power-efficient embedded processing with resilience and real-time constraints 具有弹性和实时约束的节能嵌入式处理

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273519

Liang Wang, Augusto J. Vega, A. Buyuktosunoglu, P. Bose, K. Skadron

{"title":"Power-efficient embedded processing with resilience and real-time constraints","authors":"Liang Wang, Augusto J. Vega, A. Buyuktosunoglu, P. Bose, K. Skadron","doi":"10.1109/ISLPED.2015.7273519","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273519","url":null,"abstract":"Low-power embedded processing typically relies on dynamic voltage-frequency scaling (DVFS) in order to optimize energy usage (and therefore, battery life). However, low voltage operation exacerbates the incidence of soft errors. Similarly, higher voltage operation (to meet real-time deadlines) is constrained by hard-failure rate limits. In this paper, we examine a class of embedded system applications relevant to mobile vehicles. We investigate the problem of assigning optimal voltage-frequency settings to individual segments within target workflows. The goal of this study is to understand the limits of achievable energy efficiency (performance per watt) under varying levels of system resilience constraints. To optimize for energy efficiency, we consider static optimization of voltage-frequency settings on a per-application-segment basis. We consider both linear and graph-structured workflows. In order to understand the loss in energy efficiency in the face of environmental uncertainties encountered by the mobile vehicle, we also study the effect of injecting random variations in the actual runtime of individual application segments. A dynamic re-optimization of the voltage-frequency settings is required to cope with such in-field uncertainties.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability ReDEEM:一种用于节能可靠性的异构分布式微架构

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273530

Biruk Mammo, Ritesh Parikh, V. Bertacco

{"title":"ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability","authors":"Biruk Mammo, Ritesh Parikh, V. Bertacco","doi":"10.1109/ISLPED.2015.7273530","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273530","url":null,"abstract":"Diminishing energy-efficiency returns and decreasing transistor reliability are casting shadows on semiconductor scaling. Prior research has been addressing processors' energy-efficiency and transistor reliability as orthogonal problems. However, as embedded processors become more powerful and find their way into more diverse applications, both high reliability and energy-efficiency become critical. In this work, we propose ReDEEM, a novel approach to design energy-efficient and reliable microarchitectures. Our proposed solution composes processor pipelines at runtime from redundant but heterogeneous pipeline components. Our pipeline components are loosely coupled and the control logic is decentralized so as to enable fault isolation and thereby eliminate single points of failure. We equip the microarchitecture with the ability to adapt dynamically to varying application phases by constructing energy-efficient pipelines best suited for each phase. In addition, pipeline components have power management capabilities that allow for greater energy efficiency and flexibility. Our experimental evaluation shows that our solution offers up to 60% in energy savings and can operate about 1.8x longer, when subjected to the same fault rate as a state-of-the-art reliable microarchitecture.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121640279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Modeling and power optimization of cyber-physical systems with energy-workload tradeoff 具有能量-工作负载权衡的网络物理系统建模和功率优化

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273533

Hoeseok Yang, S. Ha

引用次数: 3

Interconnect synthesis of heterogeneous accelerators in a shared memory architecture 共享内存体系结构中异构加速器的互连合成

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273540

Yu-Ting Chen, J. Cong

{"title":"Interconnect synthesis of heterogeneous accelerators in a shared memory architecture","authors":"Yu-Ting Chen, J. Cong","doi":"10.1109/ISLPED.2015.7273540","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273540","url":null,"abstract":"An accelerator-rich architecture (ARA) is composed of heterogeneous accelerators with an on-chip memory system. Compared to the general-purpose processors, an accelerator demands short and predictable latency to its local on-chip memory to satisfy its performance target. Moreover, an accelerator requires a much higher off-chip memory bandwidth than a CPU since it consumes much more data in a given time period. Therefore, a customized on-chip memory system design is one of the keys to an efficient ARA. In this work we provide a two-layer interconnect synthesis method. We first provide an optimal layer of partial crossbar that connects the heterogeneous accelerators and shared memory banks with a minimum number of switches. The second layer of interconnect tries to interleave possible conflicting long-burst memory requests for prefetching data from off-chip memory. The experimental results show that we can reduce more than 45% of the switches of the partial crossbar compared to the best known method. This further leads to 53% reduction of LUTs and 34% reduction of slice utilization on a 30-accelerator FPGA prototype. Furthermore, the performance of an ARA can be improved by 36% - 52% with a well-designed interleaved network in a real ARA prototype for medical imaging applications. This prototype also shows a 7.44x energy efficiency gain over the state-of-the-art Xeon processors.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127818425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

FreqLeak: A frequency step based method for efficient leakage power characterization in a system FreqLeak:一种基于频率阶跃的方法，用于系统中有效的泄漏功率表征

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273513

Arun Joseph, A. Haridass, C. Lefurgy, Sreekanth Pai, Spandana Rachamalla, Francesco A. Campisano

引用次数: 0

Design and analysis of 6-T 2-MTJ ternary Content Addressable Memory 6- t2 - mtj三进制内容可寻址存储器的设计与分析

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273532

Rekha Govindaraj, Swaroop Ghosh

引用次数: 6

The digital bidirectional function as a hardware security primitive: Architecture and applications 作为硬件安全原语的数字双向功能:体系结构和应用程序

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI: 10.1109/ISLPED.2015.7273536

T. Xu, M. Potkonjak

引用次数: 6