Post placement leakage reduction with stress-enhanced filler cells

Abstract

A novel methodology for the post placement leakage reduction based on employment of the stress-enhanced filler (SEF) cells was developed. Desired reduction of sub-threshold leakage in test chip silicon was achieved by placement of SEF cells close to the most leaking devices. In the standard cell rows the “optimization zones”, representing portions of the row located between two consecutive fixed cells (clock cells, etc.), were defined. Mentor Graphics' stress assessment tool was used to find the optimal locations for SEF insertion inside each zone, providing the maximal increase of threshold voltage of the leakiest transistors. Measurements performed on the processed silicon test chip have confirmed the predicted leakage reduction of 10-15 percent while keeping same electrical performance.