Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok
{"title":"A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems","authors":"Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok","doi":"10.1109/ISLPED.2015.7273496","DOIUrl":null,"url":null,"abstract":"This paper presents algorithm and digital hardware design, inspired by biological spiking neural networks, to perform unsupervised, online spike-clustering with high accuracy and low-power consumption in the context of deep-brain sensing and stimulation systems. The proposed hardware contains 1220 digital neurons and 4.86k latch-based synapses, and achieves the average sorting accuracy of 91% whereas the conventional hardware based on the Osort algorithm achieves 69% for the same datasets. Implemented in a 65nm high-Vth, the processor exhibits a footprint of 0.25mm2/ch. and a power consumption of 9.3μW/ch. at VDD of 0.3V.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISLPED.2015.7273496","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
This paper presents algorithm and digital hardware design, inspired by biological spiking neural networks, to perform unsupervised, online spike-clustering with high accuracy and low-power consumption in the context of deep-brain sensing and stimulation systems. The proposed hardware contains 1220 digital neurons and 4.86k latch-based synapses, and achieves the average sorting accuracy of 91% whereas the conventional hardware based on the Osort algorithm achieves 69% for the same datasets. Implemented in a 65nm high-Vth, the processor exhibits a footprint of 0.25mm2/ch. and a power consumption of 9.3μW/ch. at VDD of 0.3V.