CMOS开关电容变换器的分析与优化

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pub Date : 2015-07-22 DOI:10.1109/ISLPED.2015.7273535

V. Sathe, Jae-sun Seo

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引用次数: 5

摘要

能源效率继续限制数字系统的峰值计算性能。为了推动持续的能源改进，现代数字系统的设计者依靠多个更小的电压域来增强电压缩放。开关电容(SC)电压变换器是传统开关电感调节器的一个很有前途的替代品，因为它们适合于更精细的电压域的高效、完全集成的调节。然而，关于SC变换器设计的分析和优化的几个重要问题仍然没有得到解决。本文对SC变换器的输出电阻进行了全面的分析，以确定最大变换器效率的最佳开关频率和开关电阻。通过采用工业65纳米CMOS技术进行的仿真实验验证了所提出的分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis and optimization of CMOS switched-capacitor converters

Energy-efficiency continues to limit peak computational performance in digital systems. To drive continued energy-improvements, designers of modern digital systems are relying on multiple, smaller voltage domains for enhanced voltage-scaling. Switched-capacitor (SC) voltage converters are a promising alternative to traditional switched-inductor regulators due to their suitability for efficient, fully-integrated regulation of finer voltage domains. However, several important problems regarding the analysis and optimization of SC converter design remain unaddressed. This paper develops a comprehensive analysis of SC converter output resistance to establish the optimal switching frequency and switch resistance for maximum converter efficiency. The proposed analysis is validated through simulation experiments conducted using an industrial 65nm CMOS technology.

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来源期刊

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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