International Symposium for Testing and Failure Analysis最新文献_第6页

Electronics Failure Analysis Demonstrations using a Quantum Diamond Microscope 电子故障分析演示使用量子金刚石显微镜

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0007

P. Kehayias, E. Levine, A. Rodarte, J. Walraven, A. Mounce

引用次数: 0

Failure and Thermal Dissipation Analysis with Infrared Thermography 用红外热像仪分析故障和散热

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022tph1

Stephan R. Larmann

引用次数: 0

Failure Analysis Challenges for Chip Scale Packages (2022 Update) 芯片级封装的失效分析挑战(2022更新)

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022tpr1

Susan X. Li

引用次数: 0

Inspection of Charge Effect on Metal Layer by Using SCM 用单片机检测金属层电荷效应

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0355

Gyubaek Lee, Da-Hee Park, Minjung Kim

{"title":"Inspection of Charge Effect on Metal Layer by Using SCM","authors":"Gyubaek Lee, Da-Hee Park, Minjung Kim","doi":"10.31399/asm.cp.istfa2022p0355","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0355","url":null,"abstract":"\u0000 The importance of charging damage grows as the IC industry continues downward scaling. It was found that electrical test on metal pad to check contact failure, layer connection and resistance caused charging damage as serious as plasma charging. As for the side effect of it, DC charge is accumulated on the metal TEG, which causes some failure such as incomplete etch problems in the next metal fabrication. This paper provides that charge effect on metal surface is able to be verified by Scanning Capacitance Microscope (SCM). SCM has been used to analyze carrier trap on semiconductor layer in 2D mapping image as well as dopant distribution. In this paper, we will present SCM as more effective and sensitive than contact based DC-EFM (Electrostatic Force Microscope) and verify how to detect the charge on the surface of metal with a physical model based on a parasitic capacitance. It is possible to analyze MIM (Metal-Insulator-Metal) structure because permittivity of insulator is varied like MOS (Metal Oxide Semiconductor) for induced dielectric dipole polarization. Even though it is required to deposit additional insulator layer on a metal, it is highly beneficial to inspect charge effect during post-processing.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

1D-ResNet Framework for Ultrasound Signal Classification 超声信号分类的1D-ResNet框架

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0021

A. S. Nair, P. Hoffrogge, P. Czurratis, C. Hollerith, Alexander Roch, Alireza Haghighat, K. Pressel, Frank Zudock, M. Wolf, E. Kühnicke

{"title":"1D-ResNet Framework for Ultrasound Signal Classification","authors":"A. S. Nair, P. Hoffrogge, P. Czurratis, C. Hollerith, Alexander Roch, Alireza Haghighat, K. Pressel, Frank Zudock, M. Wolf, E. Kühnicke","doi":"10.31399/asm.cp.istfa2022p0021","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0021","url":null,"abstract":"\u0000 Minor flaws are becoming extremely relevant as the complexity of the semiconductor package evolves. Scanning acoustic microscopy is one analytical tool for detecting flaws in such a complex package. Minor changes in the reflected signal that could indicate a fault can be lost during image reconstruction, despite the high sensitivity. Because of recent AI (Artificial Intelligence) advancements, more emphasis is being placed on developing AI-based algorithms for high precision-automated signal interpretation for failure detection. This paper presents a new deep learning model for classifying ultrasound signals based on the ResNet architecture with 1D convolution layers. The developed model was validated on two test case scenarios. One use case was the detection of voids in the die attach, the other the detection of cracks below bumps in Flip-chip samples. The model was trained to classify signals into different classes. Even with a small dataset, experiment results confirmed that the model predicts with a 98 percent accuracy. This type of signal-based model could be extremely useful in situations where obtaining large amounts of labeled image data is difficult. Through this work we propose an intelligent signal classification methodology to automate high volume failure analysis in semiconductor devices.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Fault Analysis Approach for a High Resistance via with Nano-Probing on FIB Recess Sample and TEM Lamella 利用纳米探针对FIB凹槽样品和TEM薄片进行高电阻故障分析的新方法

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0343

Che Nan Siti Nurjatikesuma, Loo Huey Wen, Oung Pey Fen, Lee Chong Haw

引用次数: 0

Automated TEM Lamella Preparation using Remote CAD to SEM Alignment 利用远程CAD与SEM比对自动制备TEM片层

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0206

Hyun Woo Shim, Taehun Lee, J. Kwon

引用次数: 0

Absolute Temperature Thermal Mapping Methodology for Tester Applications 测试应用的绝对温度热测绘方法

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0120

B. Lai, N. Leslie, P. Sabbineni, V. Ravikumar

{"title":"Absolute Temperature Thermal Mapping Methodology for Tester Applications","authors":"B. Lai, N. Leslie, P. Sabbineni, V. Ravikumar","doi":"10.31399/asm.cp.istfa2022p0120","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0120","url":null,"abstract":"\u0000 Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122198995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Fundamentals of Nanoprobe Analysis (2022 Update) 纳米探针分析的基础(2022更新)

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022tpb1

Randal E. Mulder

引用次数: 0

Advanced Lithium-Ion Battery Failure Analysis—An Evolving Methodology for An Evolving Technology 先进的锂离子电池故障分析-一种不断发展的技术的不断发展的方法

International Symposium for Testing and Failure Analysis Pub Date : 2022-10-30 DOI: 10.31399/asm.cp.istfa2022p0051

T. A. Hayes, Adam P. Cohn, Robert M. Kasse, Hernan Sanchez

引用次数: 0