International Symposium for Testing and Failure Analysis最新文献

{"title":"Die-Level Micrometers-Deep Subsurface Imaging for Fault Isolation using Remote Bias Induced Electrostatic Force Microscopy","authors":"E. Strelcov, Lin You, Y. Obeng, J. Kopanski","doi":"10.31399/asm.cp.istfa2022p0426","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0426","url":null,"abstract":"\u0000 In recent years, scanning probe microscopy (SPM) has drawn substantial attention for subsurface imaging, since the ultrasharp AFM tip (≈ 10 nm in radius) can deliver and detect, mechanical and electrical signals right above the material’s 3D volume with which it is directly interacting. Electrostatic force microscopy, or EFM, is one of the most common atomic force microscopy (AFM) variants for electrical property characterization. In this work, we demonstrate a method to significantly improve EFM’s subsurface imaging capability. Unlike conventional EFM, where an AC bias is applied to the cantilever, we applied two out of phase AC biases to adjacent subsurface lines and image the resulting cantilever response at the surface. The resulting remote bias induced EFM (RB-EFM) amplitude shows decent contrast of metal lines with a 2.4 μm spacing buried up to 4 μm beneath the surface. This novel method may resolve lines with a horizontal spacing of less than 130 nm at such depth and wider lines to at least 6 μm in depth. In addition, the results are compared with conventional EFM and KPFM that detects subsurface structure with two independent DC biases. A COMSOL simulation model has been developed that reproduces the essential features of the measurement and explains the improvement of subsurface imaging with RB-EFM compared to other electrostatic force imaging techniques. We show, that by biasing independent lines at a small delta in frequency from the cantilever resonance, multiple line traces can be differentiated in the RB-EFM image.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analog Quiescent Current as Efficient Method for Accurate Fault Isolation in Complex Functional Failures","authors":"A. Merassi, E. Catanzaro, D. Passarella, A. Boglio","doi":"10.31399/asm.cp.istfa2022p0378","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0378","url":null,"abstract":"\u0000 Analog fault localization for functional failures is usually a very complex task, especially because a deep knowledge of all the functionalities of the device is often required. In addition, when the part is analyzed in application conditions, the interpretation of the anomalous emissions in the failed part and its link to the failing elementary component is not so obvious. The adoption of the analog quiescent current (IDDa) allows to address directly the failing elementary component inside the suspected block.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121226247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automated Labeling Infrastructure for Failure Analysis","authors":"Natalia Mathá, Konstantin Schekotihin, Matthias Bergner, Doriana Cobârzan, Marco Hudelist","doi":"10.31399/asm.cp.istfa2022p0036","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0036","url":null,"abstract":"\u0000 The development of intelligent assistants helping Failure Analysis (FA) engineers in their daily work is essential to any digitalization strategy. In particular, these systems must solve various computer vision or natural language processing problems to select the most critical information from heterogeneous data, like images or texts, and present it to the users. Modern artificial intelligence (AI) techniques approach these tasks with machine learning (ML) methods. The latter, however, require large volumes of training data to create models to solve the required problems. In most cases, enterprise clouds store vast volumes of data captured while applying various FA methods. Nevertheless, this data is useless for ML training algorithms since it is stored in forms that can only be interpreted by highly-trained specialists. In this paper, we present an approach to embedding an annotation process in the everyday routines of FA engineers. Its services can easily be embedded in existing software solutions to (i) capture and store the semantics of each data piece in machine-readable form, as well as (ii) provide predictions of ML models trained on previously annotated data to simplify the annotation task. Preliminary experiments of the built prototype show that the extension of an image editor used by FA engineers with the services provided by the infrastructure can significantly simplify and speed up the annotation process.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"7 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126041887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electro-Optical Interactions in FinFETs","authors":"Ravikumar Venkat Krishnan, Jin Jie, V. Somasundaram, R. Ng, Joel K. W. Yang, Pey Kin Leong","doi":"10.31399/asm.cp.istfa2022p0135","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0135","url":null,"abstract":"\u0000 Electrooptical investigations such as laser voltage probing (LVP) and dynamic laser stimulation (DLS) are very popular electrical fault isolation techniques (EFI) that use lasers on semiconductor circuits to study the functionality of transistors while the device is in operation. While many studies have been undertaken to understand interaction between laser and planar devices, three-dimensional devices such as FinFETs have interesting physiologies that have not been fully explored. In this work, we study the interaction of polarized light with the n-type metal oxide semiconductor (NMOS) FinFETs, experimentally and through Multiphysics simulations. We report highly directional electrooptical interactions in the FinFET. LVP signals are stronger when the laser used is polarized parallel to the fin and laser stimulation stronger when the laser used is polarized parallel to the gate. These findings affect future laser stimulation and probing investigations for EFI.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technique Selection for the Front End of Line Defect Localization in Bulk Si FA (2022 Update)","authors":"Gregory M. Johnson","doi":"10.31399/asm.cp.istfa2022tpf1","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022tpf1","url":null,"abstract":"\u0000 This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125495817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Decapsulating Small Outline Transistor Packaged Devices Using Acrylic Molding Technique","authors":"John Michael Saputil","doi":"10.31399/asm.cp.istfa2022p0398","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0398","url":null,"abstract":"\u0000 As the electronics industry moves towards miniaturization, the semiconductor industry provided packaging innovations to meet the demands for smaller footprints. One of the packaging solutions is the small outline transistor (SOT) which is widely used in various applications including automotive engine downsizing. Decapsulation of small packaged devices like a 1.3mm by 2.9mm SOT is one of the greatest challenges in failure analysis. The destructive nature of decapsulation may cause inadvertent and permanent damage, hindering further electrical verification on the unit. In this paper, a novel method for decapsulating SOT devices is presented utilizing the use of acrylic molding to avoid damage on the units during decapsulation process. Results show that the use of acrylic molding is an effective method in decapsulating SOT packaged devices maintaining die functionality, hence, addressing the decapsulation issues and risks caused by other existing decapsulation methods.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125745588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure Analysis Techniques for Detection of Copper Migration in Die Attach Film","authors":"Dubhe Cyrine Bejo, Greg Harold Posadas, Romel De Guzman, Margie Dalen Gobway","doi":"10.31399/asm.cp.istfa2022p0294","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0294","url":null,"abstract":"\u0000 Newly designed products require extensive reliability and stress testing to catch early failures due to defects during fabrication or assembly processes before they can be introduced to the market. Failure analysis plays an important role in verifying these failures and defining the root cause which will drive relevant process resolution and quality improvement. In this paper, the authors demonstrate comprehensive and innovative failure analysis techniques on leakage current localization to prove the defect mechanism of copper migration seen from the internal lead fingers into the die’s substrate on a device with chip-on-lead architecture.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Thermal Laser Stimulation (TLS) Effects on 7nm FinFET Transistor Parameters","authors":"Johns Oarethu, Zhigang Song, Patricia A. Mcginnis, Stephen Wu, Phong Tran, M. Tenney, Richard Oldrey","doi":"10.31399/asm.cp.istfa2022p0129","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0129","url":null,"abstract":"\u0000 Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124809639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AFM in SEM for Device Characterization and Defect Localization","authors":"Gregory M. Johnson, F. Hitzel","doi":"10.31399/asm.cp.istfa2022p0438","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0438","url":null,"abstract":"\u0000 The results of analyses on a commercially available 7 nm SRAM, using an in-situ AFM inside a SEM, are presented. In addition to typical results for conductive AFM, a novel method is described that uses the SEM beam to prepare a region for additional material removal, thus bringing out clearer electrical data. This would be of exceptional value for technology nodes using cobalt as a contact material. Finally, techniques making use of the current from the SEM beam as the source of current during the measurement are described. The technique may have value for well resistance measurements using in-situ structures on live product, a survey of junction health, or the localization of point defects.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Methodical Failure Analysis Approach Using Thermomechanical Analysis in Reducing Recurring Failures on iButton Modules","authors":"John Albert Austral, E. Cruz","doi":"10.31399/asm.cp.istfa2022p0298","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2022p0298","url":null,"abstract":"\u0000 The iButton temperature logger is a robust and independent system that measures temperature and records the temperature data in a non-volatile memory section. Although iButtons are a relatively mature product, failures due to Battery Depletion and Battery-On-Reset (BOR) occur. Despite the implementation of major corrective actions to improve product reliability and robustness, customer failures due to Depleted Battery and BOR have not been fully eliminated. One recent quality issue involved a high failure rate on one iButton variant at the customer’s quality control before calibration, which prompted a thorough failure analysis to nail down the real cause of failure. This paper presents methodical failure analysis (FA) steps and processes that led to the identification of failure mechanisms. As a result, the real issue was detected leading to a more accurate corrective action and device reliability.","PeriodicalId":417175,"journal":{"name":"International Symposium for Testing and Failure Analysis","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}