2015 16th International Conference on Electronic Packaging Technology (ICEPT)最新文献_第9页

Development of fine line build-up organic substrate using thin film RDL technology 利用薄膜RDL技术开发细线构筑有机衬底

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236638

Xinyu Wang, Jian Cai, Yu Chen, Cheng Li, Xi He, Shuidi Wang

{"title":"Development of fine line build-up organic substrate using thin film RDL technology","authors":"Xinyu Wang, Jian Cai, Yu Chen, Cheng Li, Xi He, Shuidi Wang","doi":"10.1109/ICEPT.2015.7236638","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236638","url":null,"abstract":"As a low cost solution to realize a fine line structure for high density chip interconnection, the thin film organic substrate that adopted the same concept as flip chip RDL (redistribution layers) technology has been developed in this study. The coarse line of a conventional substrate could be refined to a much finer distribution through the application of a thin film process. The thin film layers had been deposited on both sides of a 4-inch diameter BT substrate by Cu sputtering and electroplating. The dielectric material, was built-up by spin coating process. Daisy chain testing circuit has been designed to evaluate the bonding performance between the dummy die and the thin film substrate. The fine line trace with the 5μm/5μm line/space was electroplated on the top layer. A 7mm×7mm dummy die was then flip chip bonded to the thin film substrate with a unit size of 10mm×10mm. The resistance of the wiring traces was tested to make sure that the interconnection between the chip and the interposer is good. The result was similar to the theoretical value, indicating that the structure of interconnection was successful.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129818981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new kind of circular polarized slotted waveguide array antenna 一种新型圆极化开槽波导阵列天线

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236835

Xue-ling Jing, Zhao-Jun Zhu, Yu-zhu Wang, Yang Peng

引用次数: 5

Lifetest system for assessing reliability of high-power semiconductor laser diodes 用于评估高功率半导体激光二极管可靠性的寿命测试系统

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236748

Wenbin Liu, Taishan Wang, Chengpeng Li, Hong Xia, M. Hu, Yan Liu

{"title":"Lifetest system for assessing reliability of high-power semiconductor laser diodes","authors":"Wenbin Liu, Taishan Wang, Chengpeng Li, Hong Xia, M. Hu, Yan Liu","doi":"10.1109/ICEPT.2015.7236748","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236748","url":null,"abstract":"High power semiconductor laser diodes are widely used for fiber laser pumping, solid-state laser pumping, materials processing, cosmetic treatment, laser display, solid-state lighting and military applications. Existing and emerging applications push the technology of high-power semiconductor laser diodes to even wider range of wavelengths, higher power and brightness, lower cost of manufacturing and the most importantly, the improvement of reliability. However, the reliability assessment of multiple high-power laser diodes has been difficult and costly due to the high current, high-density heat flux, high optical intensity and the possibility of contamination in a long-term lifetest. The lack of high-performance lifetest systems has hindered the progress of high power laser diodes. In this paper, we report the design and implementation of a high-performance system for reliability testing of high-power semiconductor laser diodes. This system is capable of simultaneously aging 80 single-emitter diodes each outputting 10-20W optical power with the in-situ optical power and optical wavelength monitoring. The handling capacities are as high as 2KW and 4KW, respectively for optical power and heat dissipation. Many features are implemented to ensure correct and safe use of the system. Various temperature sensors are embedded inside the system to monitor the temperatures of the cooling water, the temperature of the air and the temperatures of the heat sinks. Flow rate of the cooling water is monitored and controlled. As required for long term lifetest, the system provides a class-100 clean environment and a controlled temperature for laser diodes under test. The system is used in multi-cell acceleration aging of high-power, high-brightness 9xxnm semiconductor laser diodes manufactured by Shenzhen Raybow Opto Inc.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"47 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121010988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The effect of micro-structure evolution in electromigration on the reliability of solder joints 电迁移过程中微结构演变对焊点可靠性的影响

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236729

Jicheng Zhang, Yangjian Xu, L. Liang, Yuanxiang Zhang, Y. Liu

引用次数: 1

Potential-dependence of additives distribution in copper electrodeposition via filling 填充铜电沉积中添加剂分布的电位依赖性

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236569

Zhipeng Chen, Wei-Xiong Luo, Ying Zhu, Ming Li, Liming Gao

引用次数: 2

Interfacial microscopic reaction mechanism of lead-free attachment material in IGBT packaging IGBT封装中无铅附着材料的界面微观反应机理

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236861

Hongyan Xu, Chunlei Wang, Libing Zheng, Huachao Fang, Ju Xu

引用次数: 0

Embedding chip into substrates with cavities for hetergeneous integration 将芯片嵌入有空腔的基板中，实现异质集成

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236758

Ming-Ai Zhang, J. Shang, Long Chen

{"title":"Embedding chip into substrates with cavities for hetergeneous integration","authors":"Ming-Ai Zhang, J. Shang, Long Chen","doi":"10.1109/ICEPT.2015.7236758","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236758","url":null,"abstract":"Technologies for the embedding of active and passive components into the multilayer substrate can effectively reduce the circuit length, improve the electrical performance and thermal properties through the designing of thermal path. It allows a large extent miniaturization of products' size and makes high density packaging enabled. In this paper, we embedded the organic interposer with flip-chip into the T-shaped cavity on the core substrate to form an embedded chip package structure. First of all, the thinned chip was flip-mounted on an organic interposer with solder bump, the interposer was fabricated with the circuit pattern as the lead-out module, and meanwhile a T-shaped cavity was machined on an organic core substrate by 355nm laser, which matches the shape of the interposer with chip. Then the interposer was placed in the T-cavity and the core substrate was covered with some prepreg layers. Next embedding chip into substrate was processed by a vacuum lamination machine. At last, laser drilling was used for blind via formation connecting to the pads on the interposer, and via metallization was implemented by vertical PTH and plating process. After the whole processes, thermal cycle test was performed. Results show that the embedded process was demonstrated successfully, and there were no cracks on the die and no voids in the embedded structure. Finally, the steady-state thermal analysis of the embedded substrate was taken to improve the thermal performance and optimum of the embedded substrate.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132561847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A new copper ink with low sintering temperature for flexible substrates 一种用于柔性基板的低烧结温度铜油墨

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236713

Yan Li, Tianke Qi, Yuanrong Cheng, F. Xiao

{"title":"A new copper ink with low sintering temperature for flexible substrates","authors":"Yan Li, Tianke Qi, Yuanrong Cheng, F. Xiao","doi":"10.1109/ICEPT.2015.7236713","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236713","url":null,"abstract":"The metal organic decomposition ink, one of the frequently-used conductive ink, has attracted more and more attentions. However, a serious drawback of the metal organic decomposition inks is that the sintering temperature is too high for the fabrication of printed electronic devices on a flexible organic substrate, such as PET film. Thus, the metal decomposition ink with low sintering temperature below 200 °C is required. It has been reported that the octylamine can effectively reduce the decomposition temperature of copper formate for metal organic decomposition ink. In this paper, we present the development of a new copper ink, which is composed of copper formate and isopropanolamine. The ink can decompose at 120 °C under nitrogen and form a conductive film. The copper organic decomposition ink was characterized by UV, FTIR and TGA. Copper film was obtained by coating the ink onto the glass and PET substrate followed by sintering at a relatively low temperature. The copper film showed a low resistance of 32.3 μΩ·cm when sintered at 135 °C, measured with a four-point probe method. The structure of copper film was characterized by XRD which consisted of pure copper. SEM showed the differences in the morphology of the copper film at various temperature.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Optimization and analysis of micro capacitive comb accelerometer 微电容梳状加速度计的优化与分析

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236793

Junchao Wang, Xiaosong Ma

引用次数: 0

Stress analysis and parametric studies for a ultralow-k chip in the flip chip process 倒装过程中超低k芯片的应力分析与参数研究

2015 16th International Conference on Electronic Packaging Technology (ICEPT) Pub Date : 2015-09-03 DOI: 10.1109/ICEPT.2015.7236679

Lin Lin, Jun Wang, Lei Wang, Wenqi Zhang

{"title":"Stress analysis and parametric studies for a ultralow-k chip in the flip chip process","authors":"Lin Lin, Jun Wang, Lei Wang, Wenqi Zhang","doi":"10.1109/ICEPT.2015.7236679","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236679","url":null,"abstract":"Using ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials become fragile because tiny pores and inclusions were introduced to reduce the dielectric constant (k). As a result, the mechanical failures in ULK materials are critical during packaging processes, such as solder reflow. In this study, the stress analysis and parametric study for a designed ULK chip under the flip chip reflow was performed by finite element method with sub-modeling technology. The microstructures on the surface of chip, including ULK materials, were homogenized to an effective thin layer and equivalent material properties were used in the global model analysis. The ULK/Cu structures under the corner joint that suffering higher stresses was analyzed by the sub-modeling method. The local model including M1 - M10 Cu/ULK connection and dielectric layers and the stresses can be achieved . Using the method, the effect of design parameters, e.g. PI opening, copper pillar diameter and Ni thickness, was examined by comparing the stress in the ultralow-k dielectric layers. The results reveal a decreased risk for a design with the smaller PI opening, larger copper pillar diameter and adding the Ni layer.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"7 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128718160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2