Stress analysis and parametric studies for a ultralow-k chip in the flip chip process

Abstract

Using ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials become fragile because tiny pores and inclusions were introduced to reduce the dielectric constant (k). As a result, the mechanical failures in ULK materials are critical during packaging processes, such as solder reflow. In this study, the stress analysis and parametric study for a designed ULK chip under the flip chip reflow was performed by finite element method with sub-modeling technology. The microstructures on the surface of chip, including ULK materials, were homogenized to an effective thin layer and equivalent material properties were used in the global model analysis. The ULK/Cu structures under the corner joint that suffering higher stresses was analyzed by the sub-modeling method. The local model including M1 - M10 Cu/ULK connection and dielectric layers and the stresses can be achieved . Using the method, the effect of design parameters, e.g. PI opening, copper pillar diameter and Ni thickness, was examined by comparing the stress in the ultralow-k dielectric layers. The results reveal a decreased risk for a design with the smaller PI opening, larger copper pillar diameter and adding the Ni layer.