Lin Zhou, Wen-Peng Xiao, Wenlong Yuan, Ming-Gao Cao, Rong Liang, Yi-Min Hu, Yan Liu, Hailin Wu
{"title":"On-line measurement and analysis of high-power LED characters in accelerated life test","authors":"Lin Zhou, Wen-Peng Xiao, Wenlong Yuan, Ming-Gao Cao, Rong Liang, Yi-Min Hu, Yan Liu, Hailin Wu","doi":"10.1109/ICEPT.2015.7236792","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236792","url":null,"abstract":"Accelerated life test is most frequent used method in electronics and optoelectronics device reliability, failure model and life prediction research. Due to lack of suitable equipment and instruments, for now, the LED properties are measured by off-line methods during the accelerated life test which require the experiment process have to be interrupted. In our work, we built a system which could carry out on-line measurement of LED properties (such as luminous flux, color temperature, junction temperature and thermal resistance) during the accelerated life test. As we all known, the structures of different LED chips (horizontal, vertical and flip) have great influence to their illuminant and thermal performance. In this study we compared the advantage and disadvantage of their performance.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125602919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wei Jiang, Yongda Hu, S. Bao, Song Lijie, Zheng Yuwei, Yongqiang Cui, Li Qiang
{"title":"Analysis on the causes of decline of MLCC insulation resistance","authors":"Wei Jiang, Yongda Hu, S. Bao, Song Lijie, Zheng Yuwei, Yongqiang Cui, Li Qiang","doi":"10.1109/ICEPT.2015.7236807","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236807","url":null,"abstract":"In this paper, based on the results of SEM and EDS analysis, I would like to share the discovery of MLCC failure due to insulation resistance. For external factors, The defects which caused by mechanical stress can lead to lack of insulation resistance. For the intrinsic factors, MLCC insulation resistance failure is due to the presence of defects, and the main defects include void in ceramic dielectric and delamination of porcelain body and inner electrode. These defects are difficult to analyze. With the help of SEM electron microscope detection, these defets can be see. The reason is the poor control of sintering process.In the test,these defects will cause the capacitor quickly form a conductive channel, finally lead to insulation resistance failure.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126610278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study of fine pitch copper pillar solder joint on HDI flexible substrate for wearable devices","authors":"K. Pun, Amandeep Singh, M. Islam, Chan Mei Shan","doi":"10.1109/ICEPT.2015.7236820","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236820","url":null,"abstract":"In the trend of miniaturization, low cost, and high performance of electronic packages, high density flip chip interconnect has been required to interface with very fine pitch chips like signal processors and multiple thin dies package, this raise a great challenge to related interconnect technology in electronic packaging for high density, small feature size, and high performance. With technological development like flip-chip thermal compression bonding (TCB), interconnects have been reduced to considerable fine pitch, but traditional diffusion bonding method likes Au-Au and Au-Sn has a disadvantage of high cost and reduced throughput for multiple die package. Contrary to this Cu pillar solder reflow have been providing an excellent throughput at reasonably low cost, but they do have pitch limitations which is normally greater than 100 11m. This paper is targeted at resolving the challenges in conjunction with the advantages of Cu pillar reflow technologies and prepare a low cost solution for fabricating module which required for multiple die and fine pitch interconnects. Study was done on flexible substrate made of 25 μm PI tape with different layer count up to 4 metal layers. The Cu pillar bump pitch was kept at 80 11m with Cu pillar height of 10-13μm and solder cap of 12-15μm (very low profile for standard reflow). Variations in substrate surface finish, pad sizes, substrate flatness were investigated thoroughly. In final, the substrate flatness is identified to be the key contributor to prevent the open solders, and the OSP is found to be the most suitable candidate to ensure good solder joint integrity, this offers a great solutions for high volume production in Compass and provides an insight to designer for upcoming production of wearable devices.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128147001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study on high thermal conductivity and thick-thin film hybrid technology of AlN substrate","authors":"Huanbei Chen, Qiushi Liang","doi":"10.1109/ICEPT.2015.7236782","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236782","url":null,"abstract":"With the trend of miniaturization high power and frequency of electronic devices, the higher performances of cooling, wiring density and lower loss for substrate have been required. Thick Film Circuits and Thin Film Circuits have their limitations on fine wiring and multilayer wiring respectively, which are difficult to simultaneously meet these requirements. In this study, thick-thin film hybrid AlN substrate with properties of high thermal conductivity, multilayer wiring and fine wiring has been researched. The thermal conductivity of AlN substrate has been improved to 190 W/mK by optimizing the preparation and it can content with the cooling requirements effectively. Thick-thin film hybrid technology is induced to meet high density wiring and lower loss. This kind of substrate can be used to High- Power T/R Module, High Speed Optical Transceiver Module and other fields.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121680525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new method of robust phosphor glass fabrication and performances for LEDs","authors":"Liang Yang, An Xie, Dan Xie, Xiayun Shu","doi":"10.1109/ICEPT.2015.7236808","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236808","url":null,"abstract":"In this paper, a simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and FE-SEM. The phosphor particles dispersed in matrix is vividly observed and their distributions are uniform. Spectrum distribution and color coordinates depended on thickness of screen printed phosphor layer coupled with blue LED chip are studied. TG analysis shows phosphor glass shows excellent thermal stability in comparison to phosphor silicon. This study opens up many possibilities for applications using the phosphor glass on a selected chip which emission is well absorbed by all phosphors. The screen printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen printing technology allows the realization of high stability and thermal conductivity for phosphor layer. And this simple phosphor glass method provides many possibilities for LED packing, including TFFC (thin film flip chip) and remote phosphor technology.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121932709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lijie Song, S. Bao, Yongda Hu, Wei Jiang, Qiang Li
{"title":"The optimization of process parameters based on the orthogonal experiments in wire bonding","authors":"Lijie Song, S. Bao, Yongda Hu, Wei Jiang, Qiang Li","doi":"10.1109/ICEPT.2015.7236790","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236790","url":null,"abstract":"Regarding the effects caused by power and time of 7476D semi-automatic bonding wire on surface of ceramic substrate wedge bonding wire performances. Orthogonal experiment named L9(34) had been designed using bonding power and bonding time to get results of pull test as the test index. After processing and analysis of test data using Statistical Package for Social Science 16.0 (SPSS16.0) software, influence degree of different factors is obtained, and the optimal technological conditions of bonding wire is obtained too, which can be further provided for the problems, causes and quality assessment of wire bonding analysis' data support. From the analysis results, influence degree of different factors is obtained, and the optimum formula for bonding wire is obtained too. Bonding output power of the first bond is the key factor that affects the results of pull test. The optimal technological conditions are obtained as follows: The influence degree of each factor is not the same: A>D>B>C; the output power of the first bond is 0.32 watt; the output power of the first bond is 0.44 watt; bonding time of the first is bond 70 millisecond; bonding time of the second bond is 100 millisecond. Development of this work is of benefit to raising quality of gold wire wedge bonding. Through the above analysis, aiming at the problem of multiple factors and multiple levels, we can use the method of orthogonal test to solve test index, so not only reduced the number of test, and obtained the optimum formula.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122481033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A rectangular coaxial line low-pass filter with simple structure","authors":"Xi Tian, Yu-zhu Wang, Tianyiyi He","doi":"10.1109/ICEPT.2015.7236692","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236692","url":null,"abstract":"In this paper, a simple structure of low-pass filter with low passband insertion loss is proposed. The filter is composed of a rectangular coaxial line and two lines of symmetrically arranged screws on the opposite sides. And a unit circle will be analyzed. Furthermore, this paper will show the realization of an order-11 low-pass filter, whose cutoff frequency is 20 GHz, based on this structure. This new-type filter have a sharp rejection, low insertion loss and relatively high power handing capacity. The simulation results indicate that the rejection is better than 40dB from 22 to 30.5 GHz and the reflection coefficient is lower than -10dB over the full pass band from 0 to 20 GHz.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125030734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation analysis of the fine pitch micro-bump formation with solder injection method","authors":"Hongwen He, Daquan Yu, Tingyu Lin, Liqiang Cao","doi":"10.1109/ICEPT.2015.7236546","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236546","url":null,"abstract":"In this paper, a new micro-bump formation process was investigated by simulation method. In detail, a solder filling fixture was fabricated to hold the solder paste or alloy over the photoresist openings. As the fixture moves along the wafer surface, the solder paste or alloy was heated up to liquid status to fill in the photoresist openings under pressure force and vacuum circumstance. Then cooled down the temperature and solidified the molten solder to form the desired bumps. Before conduct the new bumping formation process, simulation work should be done to evaluate the process practicability and validation. Emphasis was placed on the simulation process construction to demonstrate the feasibility of the new bumping technology. Different influencing factors that may affect the bumping quality were studied such as the wall thickness of the filling fixture, gap between the wafer and the filling fixture, filling pressure, movement velocity of the filling fixture, and so on. In conclusion, an optimal filling parameter was obtained based on the simulation result. Future work will concentrate on the filling tests to verify the simulation results.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131347817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Numerical simulation of heat transfer cooling down by water in microgap structure","authors":"Jiancheng Shen, Z. Wen, Jinsong Zhang","doi":"10.1109/ICEPT.2015.7236776","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236776","url":null,"abstract":"With the increase of power density in chip, the electronic products have to face the challenge of heat dissipation technology. For the heat transfer of microgap, the fluid flows through the pathway which has a large ratio between the width and depth in the cross-section and a small ratio between the length and width in the top view. The rectangular microgap was built before modeling and Fluent software was applied to simulate and analyze the temperature field. The input heat flux was 8.3 × 104 w/m2, the water flow rate was 0.32 m/s, and the inlet water temperature was 300 K. Some conclusions had been drawn as following. The temperature distribution was symmetrical to the Z axis. The temperature gradient took a radial pattern from the model center to edges. The isotherm in microgap had a “U” shape, which indicated that the water flowing in center had a better capability for heat transfer. The isotherms presented the regular onion shape of wall temperature while the microgap depth varied from 0.05 mm to 0.7 mm. Each isotherm onion diagram had a tip at the right and a bottom at the left to correspond with the water flowing path from inlet to outlet. The center of wall had been cooled down more efficiently and the low temperature region was distributed along the water flowing path. When the depth increases to be 0.9 mm and 1.1 mm, the isotherm curves were so flat that the onion shape had been disappeared. This could be contributed to the large microgap depth reduce the water flow rate. The wall temperature curve had an ascending fluctuation with the increasing of microgap depth.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125521124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hirokazu Ito, K. Hasegawa, T. Matsuki, S. Kusumoto
{"title":"Lift-off photoresists for advanced IC packaging metal paternning","authors":"Hirokazu Ito, K. Hasegawa, T. Matsuki, S. Kusumoto","doi":"10.1109/ICEPT.2015.7236829","DOIUrl":"https://doi.org/10.1109/ICEPT.2015.7236829","url":null,"abstract":"3D-TSV, 2.5D interposer, PoP and Flip-Chip wafer micro-bumping are being implemented for consumer electronic products such as mobile phones, tablets, and so on. The consumer product market trends toward smaller and thinner, and cause the IC packaging becoming more complexity. The lift-off method of the photoresist for IC packaging metal patterning has been widely used in the variety of electronic device fabrication processes such as MEMS, and LED manufacturing. The big advantages of using lift-off method are the cost saving and the process simplification. However there is a challenge that the morphology of the deposited metal pattern is difficult to be controlled. In order to achieve desired metal patterning, there are two types of novel lift-off photoresist were developed which are single-layer negative tone photoresist and double-layer positive tone photoresist. Both the photoresists show unique and well-controlled “undercut” profile which enables to form a targeted metal configuration after exposure, development and stripping process. This paper reports the key parameter of photoresist and shows how to control the undercut profile.","PeriodicalId":415934,"journal":{"name":"2015 16th International Conference on Electronic Packaging Technology (ICEPT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}