2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第3页

Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing 一种优化传感器处理的可配置容错多核系统

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875433

Markus Ulbricht, R. Syed, M. Krstic

引用次数: 2

Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiation 在Zynq SoC上实现的SHyLoC压缩IP核在重离子辐射下的TMR软错误缓解效果评估

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875281

Antonio J. Sánchez, Y. Barrios, Lucana Santos, R. Sarmiento

引用次数: 2

Preventing Scan Attack through Test Response Encryption 通过测试响应加密防止扫描攻击

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875355

Satyadev Ahlawat, Jaynarayan T. Tudu, M. Gaur, M. Fujita, Virendra Singh

{"title":"Preventing Scan Attack through Test Response Encryption","authors":"Satyadev Ahlawat, Jaynarayan T. Tudu, M. Gaur, M. Fujita, Virendra Singh","doi":"10.1109/DFT.2019.8875355","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875355","url":null,"abstract":"The strategies for breaking a cipher has been shifting towards side channel attacks which exploit the run-time physical attributes of cryptographic chips. Among the many such attacks, the scan-based attack has become a convenient approach for attackers to extract the secret information. As reported in academic research, the scan-based side-channel attacks have been successfully mounted on Advanced Encryption Standard (AES) crypto chips. On the other hand, the scan design-for-test (DfT) has become a mandatory practice for almost all the modern designs for the test, debug, and diagnosis. Therefore, the development of a secure scan test technique is very much needed, which can effectively countermeasure the scan attacks on cryptographic chips. In this paper, we propose a new countermeasure against scan attacks on AES crypto chips. The proposed countermeasure is based on the principle of test response encryption. The scan chain content can be scanned out only in encrypted form and hence cannot be analysed by an unauthorised user. The proposed countermeasure thwarts all the known scan attacks on scan design without compromising on its test capabilities. Moreover, the extra circuitry used for test response encryption is used during mission mode to achieve 2X throughput compared with the conventional iterative AES architecture.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116525208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification 基于RISC-V处理器驱动的自主系统在线测试

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875345

A. Ruospo, R. Cantoro, E. Sánchez, Pasquale Davide Schiavone, Angelo Garofalo, L. Benini

{"title":"On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification","authors":"A. Ruospo, R. Cantoro, E. Sánchez, Pasquale Davide Schiavone, Angelo Garofalo, L. Benini","doi":"10.1109/DFT.2019.8875345","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875345","url":null,"abstract":"In the last decade, a growing number of electronic devices have been designed to be deployed in safety-critical autonomous systems. Many application domains, such as autonomous vehicles, robots, nano-drones, are exploring artificial intelligence solutions to handle the increasing computation requirements. Besides, due to their safety-critical application scenarios, they are demanding for even more reliable and advanced systems. These requirements clearly entail a growing complexity in modern processors and System-on-a-Chip design, leading to new efforts in verification and testing phases. These new devices must be also compliant with emerging functional safety standards that regulate their usage during the entire lifetime. The main intent of this work is to improve the reliability of autonomous systems, providing a strategy to link the verification methodology with the testing one. Starting from an almost exhaustive verification set, it is possible to derive a different set of patterns intended for on-line testing. This achievement is gained by taking into account the constraints due to the final system application and the common requirements of the embedded devices used in autonomous systems. Experimental results are provided on an open-source RISC-V processor assembled on an autonomous nano-drone.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115774317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications 用于空间应用的可扩展和可配置多芯片SRAM封装

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875489

A. Simevski, Patryk Skoncej, C. Calligaro, M. Krstic

引用次数: 1

CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore CORE-VR:一种具有一致性和可重用性的多核低电压容错缓存

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875457

A. Choudhury, B. Sikdar

引用次数: 0

Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction 用3位突发纠错保护大字存储器免受mcu的攻击

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875396

Jiaqiang Li, P. Reviriego, Liyi Xiao, A. Klockmann

{"title":"Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction","authors":"Jiaqiang Li, P. Reviriego, Liyi Xiao, A. Klockmann","doi":"10.1109/DFT.2019.8875396","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875396","url":null,"abstract":"The increasing importance of Multiple Cell Upsets (MCU) in memories has led to the development of error correction codes that can correct multiple bit errors on nearby bits. In particular, 3-bit burst error correction codes have been recently proposed for memories with data words of up to 64 bits. In some cases, like caches, widths can be much larger than 64 bits and therefore, to protect them 3-bit burst codes with larger block sizes are needed. Most of the 3-bit burst codes presented so far are generated with a computer search program. This approach does not scale well to large word sizes. Recently an algorithmic construction has also been proposed for 3-bit burst codes that supports large word sizes. A decoding algorithm was also proposed but no implementation was provided. This paper studies the implementation of 3-bit burst error correction for large word sizes using the recently proposed algorithmic code construction. To that end, the decoding has been implemented using the algorithm proposed for those codes and a traditional syndrome decoding and both have been compared to a SEC-DED code. The results show that syndrome decoding is more efficient than the ad-hoc algorithm. Compared to a SEC-DED decoder, implementing 3-bit burst correction decoder requires approximately an increase of 2x in area, 3x in power and 20–30% in delay for word sizes of 128, 256 and 512 bits. Therefore, the impact is significant even when using the most efficient decoder implementation.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Testing of In-Memory-Computing 8T SRAMs 内存计算8T ram的测试

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875487

Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun

引用次数: 10

Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing 基于忆阻器传感的容错光伏阵列修复电路

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875467

Luca Gnoli, Giuseppe Carnicelli, A. Parisi, Luca Urbinati, Burim Kabashi, Fabio Michieletti, Sebastian Ignacio Peradotto Ibarra, M. Vacca, M. Graziano, J. Mathew, M. Ottavi

{"title":"Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing","authors":"Luca Gnoli, Giuseppe Carnicelli, A. Parisi, Luca Urbinati, Burim Kabashi, Fabio Michieletti, Sebastian Ignacio Peradotto Ibarra, M. Vacca, M. Graziano, J. Mathew, M. Ottavi","doi":"10.1109/DFT.2019.8875467","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875467","url":null,"abstract":"Solar energy is one of the most important sources of renewable energy. Photovoltaic arrays are a widely employed systems used to harvest solar energy. In such systems, the presence of faulty cells negatively affect the energy production of the entire array. The design of fault tolerant solar arrays is therefore attracting a growing interest. In this work, we propose a hardware implementation of a fault-recovery algorithm for solar cell arrays. The proposed system detects cells with degraded performance using a memristor as sensing device. With the aim of improving energy production efficiency, the connections among solar cells are reconfigured according to the array health status. The designed system automatically activates spare cells in the segments of the array to eventually increase energy production. The proposed solution can be adapted to arrays of any size and be applied to different types of solar cells. We show through simulations that the solution here proposed significantly increases the energy production in presence of faults.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells 基于灰度编码的低冗余双纠错点码4位多单元64位存储器

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875283

Shanshan Liu, P. Reviriego, K. Namba, S. Pontarelli, Liyi Xiao, F. Lombardi

{"title":"Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells","authors":"Shanshan Liu, P. Reviriego, K. Namba, S. Pontarelli, Liyi Xiao, F. Lombardi","doi":"10.1109/DFT.2019.8875283","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875283","url":null,"abstract":"Non-volatile emerging Multilevel Cell (MLC) memories (such as magneto electric, magnetic resistive, memristor-based and phase change memories) are attractive to increase density. A key advantage of these memories is that they can store several bits per cell by using different levels. This however reduces the margins against noise and other effects and can lead to larger error rates. Errors in MLC memories are usually limited to magnitude-2 levels, and thus corrupt one or two bits per cell when using a Gray mapping from levels to bits. This enables the use of codes that can correct those error patterns in a memory cell instead of codes that correct all possible patterns in the cell, thus reducing complexity and cost. In this paper, the case of a 64 data bit memory built using memory cells that can store four bits and suffer up to double bit errors per cell is considered. Several (72, 64) Spotty codes that can correct double bit errors in 4-bit cells are designed and evaluated. The new codes require fewer parity bits than existing Spotty codes or symbol-based codes such as Hong-Patel codes. Therefore, they reduce the size of the memory while having encoding and decoding complexity similar to existing alternative codes.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127793837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3