Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications

Abstract

Space applications constantly require integration of more processing capabilities and greater memory capacity, at reduced weight and power consumption. The IHP 130 nm technology is a commercially-qualified and radiation-assessed technology which is sufficiently aggressive for the conservative approach in the space area. In this process node we realize a rad-hard 16Mbit Multi-Chip Module (MCM) SRAM with improved characteristics in comparison to competitor SRAMs. Moreover, the real novelty is the scalable master-slave architecture of the System-in-Package (SiP) with Error Detection and Correction (EDAC), and scrubbing mechanisms which are now at the SiP level. Furthermore, the width of the word size is configurable. On the other side, we conduct a large number of fault injection campaigns in order to early investigate the SiP reliability. High error resilience and significantly reduced number of interrupt requests for error recovery are observed.