Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells

Non-volatile emerging Multilevel Cell (MLC) memories (such as magneto electric, magnetic resistive, memristor-based and phase change memories) are attractive to increase density. A key advantage of these memories is that they can store several bits per cell by using different levels. This however reduces the margins against noise and other effects and can lead to larger error rates. Errors in MLC memories are usually limited to magnitude-2 levels, and thus corrupt one or two bits per cell when using a Gray mapping from levels to bits. This enables the use of codes that can correct those error patterns in a memory cell instead of codes that correct all possible patterns in the cell, thus reducing complexity and cost. In this paper, the case of a 64 data bit memory built using memory cells that can store four bits and suffer up to double bit errors per cell is considered. Several (72, 64) Spotty codes that can correct double bit errors in 4-bit cells are designed and evaluated. The new codes require fewer parity bits than existing Spotty codes or symbol-based codes such as Hong-Patel codes. Therefore, they reduce the size of the memory while having encoding and decoding complexity similar to existing alternative codes.