2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第2页

Predicting Single Event Effects in DRAM 预测DRAM中的单事件效应

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875328

Donald Kline, Stephen Longofono, R. Melhem, A. Jones

{"title":"Predicting Single Event Effects in DRAM","authors":"Donald Kline, Stephen Longofono, R. Melhem, A. Jones","doi":"10.1109/DFT.2019.8875328","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875328","url":null,"abstract":"The ability to leverage commodity memory in harsh environments due to radiation has the potential advance computing capability for aerospace and nuclear applications, among others. In this work, we provide the first demonstration of the existence of a small number of weak cells to single event effects for DDR3 memory when exposed to radiation. Thus, a high proportion of single event faults are actually not entirely random and can be predicted with high accuracy. We also demonstrate a classification of single event effects into predictable single cell, unpredictable single cell, and correlated multi-cell persistent faults, the latter due to latch-up effects. We further show that through classification, we can partition faults, which allows the development of a holistic framework to provide enhanced protection of the DRAM memory. This framework leverages a fault map with bit sparing to protect against faults from weak cells in conjunction with Chipkill ECC to effectively correct chip-level and random errors. This protection provides a potential path to the use of commodity DRAM memory in high radiation environments with extremely low fault rates. Our results, based on data from a multi-day radiation beam experiment, indicate a reduction in uncorrectable bit error rate for rows containing a weak cell by a factor of $geq 10^{7}$ compared to Chipkill alone.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analog Test Interface for IEEE 1687 Employing Split SAR Architecture to Support Embedded Instrument Dependability Applications 采用分割SAR架构的IEEE 1687模拟测试接口支持嵌入式仪器可靠性应用

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875372

J. Pathrose, L. V. D. Logt, H. Kerkhoff

引用次数: 0

A State Assignment Method to Improve Transition Fault Coverage for Controllers 一种提高控制器过渡故障覆盖率的状态分配方法

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875322

Masayoshi Yoshimura, Yukihiko Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa

引用次数: 2

Efficient Error-Tolerant Quantized Neural Network Accelerators 高效容错量化神经网络加速器

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875314

Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, M. Kumm, P. Zipf, K. Vissers

{"title":"Efficient Error-Tolerant Quantized Neural Network Accelerators","authors":"Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, M. Kumm, P. Zipf, K. Vissers","doi":"10.1109/DFT.2019.8875314","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875314","url":null,"abstract":"Neural Networks are currently one of the most widely deployed machine learning algorithms. In particular, Convolutional Neural Networks (CNNs), are gaining popularity and are evaluated for deployment in safety critical applications such as self driving vehicles. Modern CNNs feature enormous memory bandwidth and high computational needs, challenging existing hardware platforms to meet throughput, latency and power requirements. Functional safety and error tolerance need to be considered as additional requirement in safety critical systems. In general, fault tolerant operation can be achieved by adding redundancy to the system, which is further exacerbating the computational demands. Furthermore, the question arises whether pruning and quantization methods for performance scaling turn out to be counterproductive with regards to fail safety requirements. In this work we present a methodology to evaluate the impact of permanent faults affecting Quantized Neural Networks (QNNs) and how to effectively decrease their effects in hardware accelerators. We use FPGA-based hardware accelerated error injection, in order to enable the fast evaluation. A detailed analysis is presented showing that QNNs containing convolutional layers are by far not as robust to faults as commonly believed and can lead to accuracy drops of up to 10%. To circumvent that, we propose two different methods to increase their robustness: 1) selective channel replication which adds significantly less redundancy than used by the common triple modular redundancy and 2) a fault-aware scheduling of processing elements for folded implementations.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A Fault-Tolerant MPSoC For CubeSats 用于立方体卫星的容错MPSoC

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875417

C. Fuchs, Pai H. Chou, X. Wen, N. Murillo, G. Furano, S. Holst, A. Tavoularis, Shyue-Kung Lu, A. Plaat, K. Marinis

{"title":"A Fault-Tolerant MPSoC For CubeSats","authors":"C. Fuchs, Pai H. Chou, X. Wen, N. Murillo, G. Furano, S. Holst, A. Tavoularis, Shyue-Kung Lu, A. Plaat, K. Marinis","doi":"10.1109/DFT.2019.8875417","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875417","url":null,"abstract":"We present the implementation of a fault-tolerant MP-SoC for very small satellites (<100kg) based upon commercial components and library IP. This MPSoC is the result of a codesign process and is designed as an ideal platform for software-implemented fault-tolerance measures. It enforces strong isolation between processors, and combines fault-tolerance measures across the embedded stack within an FPGA. This allows us to assure robustness for a satellite on-board computer consisting of modern semiconductors manufactured in fine technology nodes, for which traditional fault-tolerance concepts are ineffective. We successfully implemented this design on several Xilinx UltraScale and UltraScale+ FPGAs with modest utilization. We show that a 4-core implementation is possible with just 1.93 $W$ of total power consumption, which for the first time enables true fault-tolerance for very small spacecraft such as CubeSats. For critical space missions aboard heavier satellites, we implemented an MPSoC-variant for the space-grade XQRKU060 part together with the Xilinx Radiation Testing Consortium. The MPSoC was developed for a 4-year ESA project. It can satisfy the high performance requirements of future scientific and commercial space missions at low cost while offering the strong fault-coverage necessary for platform control for missions with a long duration.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125160081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs 基于sram - fpga的多相滤波器抽取器可靠性评估

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875316

Zhen Gao, Jinhua Zhu, Lina Yan, Tong Yan, P. Reviriego

{"title":"Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs","authors":"Zhen Gao, Jinhua Zhu, Lina Yan, Tong Yan, P. Reviriego","doi":"10.1109/DFT.2019.8875316","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875316","url":null,"abstract":"Decimation is widely used in digital communication systems to reduce the oversampling rate of the base band signal. The structure of Poly Phase Filters (PPFs) provides an efficient implementation of the decimator. This paper studies the effects of Single Event Upsets (SEUs) on PPFs based decimators implemented on SRAM-FPGAs. Fault injection experiments are performed to evaluate the reliability of the decimator to SEUs on filter coefficients and on the configuration memory. For the first part, experiment results show that only SEUs on the two most significant bits would cause non negligible SNR loss in the output. For SEUs on the essential bits in the configuration memory, about 20% of them would affect the results, among which 70% of the SEUs would cause negligible SNR loss. The percentage of SEUs that cause a SNR loss larger than 5dB are 7%, 13% and 16% for decimation rates of 16, 8 and 4, respectively. This can be explained as the decimator is composed of a number of parallel filters that is equal to the decimation rate, and each filter contributes a fraction of the final output. Therefore, a SEU on one filter would not cause large degradation to the decimated signal, and the larger the decimation rate is, the smaller the degradation of decimated signal introduced by the SEU.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127079873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking 通过残差检测保护RSA硬件加速器不受差分故障分析的影响

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875320

Ana Lasheras, R. Canal, Eva Rodríguez, Luca Cassano

引用次数: 1

High Performance Memory Repair 高性能内存修复

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875490

F. Merchant, Anandraj Devarajan, A. Basu, David Ashen, Brandon Yelton, Prashant D. Joshi

引用次数: 0

Co-relation Scan Attack Analysis (COSAA) on AES: A Comprehensive Approach AES的相关扫描攻击分析(COSAA):一种综合方法

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875272

Dipojjwal Ray, Siddharth Singh, Sk Subidh Ali, S. Biswas

引用次数: 7

On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA 基于sram的FPGA上卷积神经网络实现的可靠性研究

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2019-10-01 DOI: 10.1109/DFT.2019.8875362

B. Du, S. Azimi, C. D. Sio, Ludovica Bozzoli, L. Sterpone

{"title":"On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA","authors":"B. Du, S. Azimi, C. D. Sio, Ludovica Bozzoli, L. Sterpone","doi":"10.1109/DFT.2019.8875362","DOIUrl":"https://doi.org/10.1109/DFT.2019.8875362","url":null,"abstract":"In recent years, topics around machine learning and artificial intelligence (AI) have (re-)gained a lot of interest due to high demand in industrial automation applications in various areas such as medical, automotive and space and the increasing computational power offered by technology advancements. One common task for these applications is object recognition/classification whose input is usually an image taken from camera and output is whether an object is present and the class of the object. In industrial pipeline, this task could be used to identify possible defects in products; in automotive application, such task could be deployed to detect pedestrians for Advanced Driver-Assistance Systems (ADAS). When the task is safety-critical as in automotive application, the reliability of the task implementation is crucial and has to be evaluated before final deployment. On the other hand, Field Programmable Gate Array (FPGA) devices are gaining increasing attention in the hardware acceleration part for machine learning applications due to their high flexibility and increasing computational power. When the SRAM-based FPGA is considered, Single Event Upset (SEU) in configuration memory induced by radiation particle is one of the major concerns even at sea level. In this paper, we present the fault injection results on a Convolutional Neural Network (CNN) implementation on Xilinx SRAM-based FPGA which demonstrate that though there exists built-in redundancy in CNN implementation one SEU in configuration memory can still impact the task execution results while the possibility of Single Event Multiple Upsets (SEMU) must also be taken into consideration.","PeriodicalId":415648,"journal":{"name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129880402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17