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2018 International Conference on Electronics, Information, and Communication (ICEIC)最新文献

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31% Reduction of power consumption using active inductor at TX and AC termination at RX for a low-power post-LPDDR4 interfaces 对于低功耗后lpddr4接口，在TX处使用有源电感，在RX处使用交流端接，功耗降低31%
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330708
Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Choonghwan Lee, Chulwoo Kim
{"title":"31% Reduction of power consumption using active inductor at TX and AC termination at RX for a low-power post-LPDDR4 interfaces","authors":"Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Choonghwan Lee, Chulwoo Kim","doi":"10.23919/ELINFOCOM.2018.8330708","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330708","url":null,"abstract":"A power reduction scheme that uses AC termination at RX and a TX output driver with an active inductor part (AIP) is proposed for a point-to-point post-LPDDR4 interface at 8 Gb/s. AC termination at the receiver I/O can reduce the power consumption by preventing DC power loss. However, this does not match the 50Ω termination, resulting in inter symbol interference (ISI). The proposed AIP in the TX output driver reduces the low-frequency gain and the ISI due to AC termination. This reduces the jitter caused by AC termination of the RX and greatly improves the eye-opening. In this paper, the AC termination at the RX and the AIP in the TX were implemented in a 28-nm CMOS process and operated at 8 Gb/s with a 3 inch FR4 microstrip line. The proposed transceiver chip achieves a peak-to-peak jitter of 43.6 ps and power reduction of 31% compared with chips without AC termination and AIP.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"428 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115646958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An estimation of road surface conditions using participatory sensing 参与式传感对路面状况的估计
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330721
Yukie Ikeda, M. Inoue
{"title":"An estimation of road surface conditions using participatory sensing","authors":"Yukie Ikeda, M. Inoue","doi":"10.23919/ELINFOCOM.2018.8330721","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330721","url":null,"abstract":"When natural disasters occur, some roads could be blocked and cannot be used. Road surface conditions also deteriorate. Thus, collecting and providing the information on usable roads and road surface conditions can allow people to be evacuated safely. In this study, we proposed an estimation system of the road surface conditions by collecting accelerometer data from pedestrians' smartphones. The method estimates whether the road surface condition is a flat pavement road, a rough road, a slope or a stair by using supervised machine learning method. From the results of experiment, we found that the system can estimate six types of road surface conditions with a high accuracy when training the model with the data from the users.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114391460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Epileptic seizure detection for multi-channel EEG with deep convolutional neural network 基于深度卷积神经网络的多通道脑电图癫痫发作检测
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330671
Chulkyun Park, Gwangho Choi, Junkyung Kim, Sangdeok Kim, Tae-Joon Kim, Kyeongyuk Min, K. Jung, Jongwha Chong
{"title":"Epileptic seizure detection for multi-channel EEG with deep convolutional neural network","authors":"Chulkyun Park, Gwangho Choi, Junkyung Kim, Sangdeok Kim, Tae-Joon Kim, Kyeongyuk Min, K. Jung, Jongwha Chong","doi":"10.23919/ELINFOCOM.2018.8330671","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330671","url":null,"abstract":"A new epileptic seizure detection method based on deep convolutional network is proposed. The proposed network is designed for multi-channel EEG signals and considers spatio-temporal correlation, a feature in epileptic seizure detection, using 1D and 2D convolutional layers. 1D convolutional layer considers temporal evolution of the EEG signal of each channel and 2D convolutional layers considers spatial relationships between EEG channels. We make datasets for training and test by extracting the EEG segments from CHB-MIT EEG Scalp database and SNUH-HYU EEG database: the recordings of long-term EEG monitoring at Seoul National University Hospital and Children's Hospital Boston. Our model is trained and tested using the EEG segments with varying durations. We also investigate the effect of artifact elimination on epileptic seizure detection by applying a low-pass filter to the EEG signals. Our model achieves 90.5% prediction accuracy with SNUH-HYU EEG dataset.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Recognition method of license plate for black box video using Apache Kafka 基于Apache Kafka的黑箱视频车牌识别方法
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330552
Seonghu Hong, Sang-Won Jung, Chang-Sung Jeong
{"title":"Recognition method of license plate for black box video using Apache Kafka","authors":"Seonghu Hong, Sang-Won Jung, Chang-Sung Jeong","doi":"10.23919/ELINFOCOM.2018.8330552","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330552","url":null,"abstract":"With the increase in the number of images from various channels such as a vehicle's black box, CCTV and drone, the amount of data related to the vehicles and the traffic situations is also explosively increasing. Also, the greatly increased image data analysis is further emphasizing the importance of large-scale image data processing. In this regard, this study proposed and designed a distribution system using Kafka. For high-speed processing of data, black box image frames were distributed to several nodes using Kafka, a real-time message distribution processing system. Moreover, by setting the frame of black box image as input to each node, the localization of car license plates through image processing, and segmented character recognition were explored.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122609366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Spatial capacity of LTE-based V2V communication 基于lte的V2V通信空间容量
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330572
Yosub Parkt, Sungwoo Weon, Incheol Hwang, Haesoon Lee, Jiyeon Kim, D. Hong
{"title":"Spatial capacity of LTE-based V2V communication","authors":"Yosub Parkt, Sungwoo Weon, Incheol Hwang, Haesoon Lee, Jiyeon Kim, D. Hong","doi":"10.23919/ELINFOCOM.2018.8330572","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330572","url":null,"abstract":"This paper presents a new performance metric, called spatial capacity, in long-term evolution (LTE)-based vehicle-to-vehicle (V2V) communication. The spatial capacity is defined as the the total amount of bits that can be successfully delivered in a unit km and 1 s. Since this metric incorporates vehicle user equipment (VUE) density, message size, and reliability simultaneously, this is useful to show the comprehensive understanding of V2V network. Numerical results show the two-dimensional contour graph of traditional reliability and spatial capacity with respect to VUE density and message size. We can see the obvious difference between them that the growth of VUE density and message size always degrades the reliability; while it increases the spatial capacity to some extent.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116708577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low search power and high reliability 13T-4R MTJ based nonvolatile ternary content-addressable memory 低搜索能力和高可靠性基于13T-4R MTJ的非易失性三元内容可寻址存储器
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330716
Hyun-Kook Park, Byungkyu Song, Seong-ook Jung
{"title":"Low search power and high reliability 13T-4R MTJ based nonvolatile ternary content-addressable memory","authors":"Hyun-Kook Park, Byungkyu Song, Seong-ook Jung","doi":"10.23919/ELINFOCOM.2018.8330716","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330716","url":null,"abstract":"Nonvolatile ternary content addressable-memory (NV-TCAM) has been widely researched because of its great advantages, such as, zero standby power consumption and compact area. However, previous NV-TCAMs suffer from process variation, DC current, and leakage current, leading to the search and write reliabilities degradation and high power consumption. In this paper, we propose a novel 13T-4R NV-TCAM cell with fully symmetric structure and a current limiter which improves the DC and leakage current problems of previous NV-TCAM cells. The proposed scheme is verified using HSPICE Monte Carlo simulation with 22-nm CMOS process and industry mimic MTJ model. The simulation results prove that the proposed scheme reduces the DC current by more than 60% and eliminates the leakage current, leading to the large power saving, while satisfies the target search yield of 4σ.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128450822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cycle-accurate full system simulation for CPU+GPU+HBM computing platform 周期精确的全系统仿真CPU+GPU+HBM计算平台
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330603
Yoonah Paik, Miseon Han, Kyu Hyun Choi, Minseong Kim, S. Kim
{"title":"Cycle-accurate full system simulation for CPU+GPU+HBM computing platform","authors":"Yoonah Paik, Miseon Han, Kyu Hyun Choi, Minseong Kim, S. Kim","doi":"10.23919/ELINFOCOM.2018.8330603","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330603","url":null,"abstract":"Nowadays GPUs have evolved into a general purpose computing platform that can handle large amounts of data, and they began to be integrated with CPUs in one chip to avoid data transfer bottleneck and reduce its required energy. Furthermore, HBM works with the integrated CPU and GPU for providing high memory throughput from lower-level memories while preserving energy efficiency for data transfer. In order to study and develop such systems in academia and industry, their cycle-accurate full system simulators became necessary, but they are not available in public. In this paper, we introduce the simulator that is adapted and integrated from several well-known simulators, i.e., PTLSim for CPU, GPGPU-Sim for GPU and DRAMSim2 for HBM. Our evaluation result showed that our simulation speed reaches 72.76% of the GPU+HBMsimulator.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115159335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sensing voltage compensation circuit for low-power dram bit-line sense amplifier 小功率dram位线感测放大器的感测电压补偿电路
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330545
S. Kim, Tae Woo Oh, Seong-ook Jung
{"title":"Sensing voltage compensation circuit for low-power dram bit-line sense amplifier","authors":"S. Kim, Tae Woo Oh, Seong-ook Jung","doi":"10.23919/ELINFOCOM.2018.8330545","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330545","url":null,"abstract":"As the DRAM process technology scales down, the offset voltage caused by the VTH mismatch between the Latch Transistors of Bit-Line Sense Amplifier (BLSA) tends to increase further. This offset voltage eventually leads to a data read failure by reducing the sensing voltage. To solve this problem, various types of offset cancellation BLSA have been studied. In addition to the offset voltage, the sensing noise between adjacent bit lines is another major cause of reduced sensing voltage. The solution to this problem is also necessary as the minimum feature size of the DRAM cell decreases. In this paper, we propose a Sensing Voltage Compensation (SVC) circuit for DRAM BLSA that can solve both problems simultaneously.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114069761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Pulsed PMOS sense amplifier for high speed single-ended SRAM 用于高速单端SRAM的脉冲PMOS感测放大器
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330662
Juhyun Park, Hanwool Jeong, Seong-ook Jung
{"title":"Pulsed PMOS sense amplifier for high speed single-ended SRAM","authors":"Juhyun Park, Hanwool Jeong, Seong-ook Jung","doi":"10.23919/ELINFOCOM.2018.8330662","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330662","url":null,"abstract":"In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAM has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22-nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114380103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
IR-UWB radar-based near-field head rotation movement sensing under fixed body motions 基于IR-UWB雷达的近场头部旋转运动传感
2018 International Conference on Electronics, Information, and Communication (ICEIC) Pub Date : 2018-04-02 DOI: 10.23919/ELINFOCOM.2018.8330555
Sunghwa Lee, Jiwon Seo
{"title":"IR-UWB radar-based near-field head rotation movement sensing under fixed body motions","authors":"Sunghwa Lee, Jiwon Seo","doi":"10.23919/ELINFOCOM.2018.8330555","DOIUrl":"https://doi.org/10.23919/ELINFOCOM.2018.8330555","url":null,"abstract":"In this study, we propose a method to measure a head rotation movement using an impulse radio ultra-wideband (IR-UWB) radar. The method modifies the pulse Doppler processing technique to extract a specific one-dimensional array, which represents the time of arrival (TOA) information of the head motion, from a frame buffer. Head movement sensing can be utilized to differentiate an intended human motion from an unintended head motion. A human interface device can also utilize head movement information.","PeriodicalId":413646,"journal":{"name":"2018 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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