2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs 基于fpga内置自检的软核嵌入式处理器

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2010-03-07 DOI: 10.1109/SSST.2010.5442812

Bradley F. Dutton, C. Stroud

引用次数: 9

Reliability and Performance Analysis of FPGA-Based Fault Tolerant System 基于fpga的容错系统可靠性与性能分析

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.27

Ryoji Noji, S. Fujie, Yuki Yoshikawa, H. Ichihara, Tomoo Inoue

引用次数: 12

Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes 基于非二进制低密度奇偶校验码的多单元闪存错误控制编码

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.25

Yuu Maeda, H. Kaneko

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引用次数: 67

Minimizing Observation Points for Fault Location 减少故障定位的观察点

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.56

Snehal Udar, D. Kagaris

引用次数: 15

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors 影响自供电可穿戴传感器能量采集电路的故障并发检测

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.39

M. Omaña, M. Marzencki, R. Specchia, C. Metra, B. Kaminska

引用次数: 1

Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power 控制磁路:时钟结构如何影响逻辑正确性和功耗

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.44

A. Dingler, M. Siddiq, M. Niemier, X. Sharon Hu, M. Alam, G. Bernstein, W. Porod

引用次数: 11

Transient Error Detection and Recovery in Processor Pipelines 处理器管道中的瞬态错误检测与恢复

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.38

S. Z. Shazli, M. Tahoori

引用次数: 12

Are Robust Circuits Really Robust? 稳健电路真的稳健吗?

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.28

S. Hellebrand, Marc Hunger

{"title":"Are Robust Circuits Really Robust?","authors":"S. Hellebrand, Marc Hunger","doi":"10.1109/DFT.2009.28","DOIUrl":"https://doi.org/10.1109/DFT.2009.28","url":null,"abstract":"Nanoscale systems are characterized by increasing parameter variations as well as an increasing susceptibility to soft errors. Transient errors during system operation are no longer restricted to memories but also affect random logic, and robust circuit design has thus become a major concern for system developers. Self-checking circuits rely on redundancy to detect and compensate errors on-line. They are usually designed to reach the totally self-checking goal (TSC), i.e. an error is detected as soon as it corrupts the system data for the first time. However, during synthesis and optimization self-checking properties can be destroyed. This presentation shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. While fault-secureness and self-testability can be verified by using standard ATPG tools for appropriate test benches, the analysis of strongly fault-secure circuits is more challenging. Here it must be proven that the circuits have a secure behavior even in the presence of fault accumulation, which requires the analysis of all possible fault sequences. To speed up the complex analysis of multiple faults we develop rules to derive detectability or redundancy information for multiple faults from the respective information for single faults. If a circuit cannot be proven to be fault-secure, the proposed method allows grading the “extent” of strong fault-secureness given by the implementation.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113960275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points 通过更多地使用功能触发器来驱动控制点，减少BIST的测试点面积

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.33

Joon-Sung Yang, B. Nadeau-Dostie, N. Touba

引用次数: 8

On-chip Generation of the Second Primary Input Vectors of Broadside Tests 侧舷测试第二主输入向量的片上生成

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.12

I. Pomeranz, S. Reddy

引用次数: 7