2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献_第6页

Error Correction Codes for SEU and SEFI Tolerant Memory Systems SEU和SEFI容错存储器系统的纠错码

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.8

S. Pontarelli, G. Cardarilli, M. Re, A. Salsano

引用次数: 9

Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories 基于RRNS码的混合存储器簇容错算法

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.37

N. Haron, S. Hamdioui

引用次数: 11

Challenges in Delay Testing of Integrated Circuits 集成电路延迟测试的挑战

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.53

D. Walker

引用次数: 0

Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? 功能测试能否实现低成本的NoC故障全覆盖?

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.62

M. Lubaszewski

{"title":"Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?","authors":"M. Lubaszewski","doi":"10.1109/DFT.2009.62","DOIUrl":"https://doi.org/10.1109/DFT.2009.62","url":null,"abstract":"The advent of the system-on-chip (SoC) technology and the integration of multiple cores and Networkon-Chip (NoC) on a single die brought new challenges in terms of testability. Defining an efficient and complete test strategy for such a new kind of system architecture is still an open problem. The test of NoC-based multicore chips is generally divided into the test of cores and the test of the communication infrastructure (network). The test of cores is usually based on the reuse of the NoC as Test Access Mechanism (TAM) to reduce area overhead and test time. As a result, the testing of the communication infrastructure is essential to guarantee the reliability of the entire system. Test approaches for the detection of faults in the communication infrastructure have based their strategies on functional, scan or BIST-based testing. All existing approaches complement each other, in the sense that none can fully cover the faults that may affect all routers and interconnects of the network. Some of the existing approaches target faults in the routers, while others cope with faults on interconnects. The refereed fault models differ from one work to another, both in terms of abstraction level (functional, RT or logic level) and of covered parts (FIFOs, registers, multiplexers, routing logic, interconnect links). This talk focuses on the functional testing of the NoC infrastructure. Herein, we are seeking for the integration of the test of interconnects and routers, at the lowest possible cost. Therefore, a manufacturing test strategy is proposed, that considers more realistic, logic level fault models, and attempts to fully cover faults that affect both the router logic and the communication channel wires. A functional-based approach is preferred, to reduce NoC re-design costs and to provide at-speed testing. However, scan and BISTbased approaches may be required to enhance both fault coverage and test application time.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116221713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors 负载认知影响分析及其在现代微处理器错误检测和容错中的应用

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.64

Y. Makris

{"title":"Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors","authors":"Y. Makris","doi":"10.1109/DFT.2009.64","DOIUrl":"https://doi.org/10.1109/DFT.2009.64","url":null,"abstract":"The objective of the research presented in this talk is to investigate the relative importance of errors in a modern microprocessor based on the impact that they incur on the execution of typical workload. Such information can prove immensely useful in allocating resources to enhance on-line testability and error resilience through concurrent error detection/correction methods. Indeed, modern microprocessors exhibit an inherent effectiveness in suppressing a significant percentage of errors and preventing them from interfering with correct program execution (i.e. application-level masking). Therefore, understanding and leveraging the correlation between low-level errors and their instruction-level impact is crucial towards developing cost-effective mitigation methods. To this end, I will first report on an extensive fault simulation infrastructure that we developed around a superscalar, dynamicallyscheduled, out-of-order, Alpha-like microprocessor, which supports execution of SPEC2000 integer benchmarks and enables the aforementioned correlation study. Then, I will demonstrate the utility of this information in developing cost-effective concurrent error detection and soft error mitigation methods for modern microprocessors. Finally, I will discuss the application of workload-cognizant impact analysis in identifying and dealing with faults that do not affect functional correctness but simply slow down program execution in modern microprocessors (i.e. performance faults).","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low DPM: Why Do We Need it and What Does it Cost! 低DPM:我们为什么需要它，它的成本是什么?

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.66

Sandeep P. Kumar

引用次数: 0