On-chip Generation of the Second Primary Input Vectors of Broadside Tests

Abstract

Broadside tests are two-pattern scan-based tests for delay faults. One of the complications that occur in relation to the application of broadside tests from an external tester is the need to change the primary input vector applied to the circuit at-speed during the test. We explore a solution to this problem where the second primary input vector of every test is produced on chip. The important features of the proposed solution are: (1) it achieves the same fault coverage as a deterministic test set; (2) on-chip area overhead can be kept low; and (3) the part of the test data that needs to be stored externally can be compacted to reduce its storage requirements.