2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献_第2页

A Novel Hardened Design of a CMOS Memory Cell at 32nm 一种新型32纳米CMOS存储单元硬化设计

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.18

Sheng Lin, Yong-Bin Kim, F. Lombardi

引用次数: 4

Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms 分析不同容错机制的形式化验证和测试工作

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.23

Meng Zhang, Anita Lungu, Daniel J. Sorin

{"title":"Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms","authors":"Meng Zhang, Anita Lungu, Daniel J. Sorin","doi":"10.1109/DFT.2009.23","DOIUrl":"https://doi.org/10.1109/DFT.2009.23","url":null,"abstract":"Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resources in the form of time, money, and engineering effort during the process [1]. Therefore, it is important to take into account the design verification (such as through formal verification) effort and chip testing effort when we design a system. This paper analyzes the impact on formal verification effort and testing effort due to adding different fault tolerance mechanisms to baseline systems. By comparing the experimental results of different designs, we conclude that re-execution (time redundancy) is the most efficient mechanism when considering formal verification and testing efforts together, followed by parity code, dual modular redundancy (DMR), and triple modular redundancy (TMR). We also present the ratio of verification effort to testing effort to assist designers in their trade-off analysis when deciding how to allocate their budget between formal verification and testing. Particularly, we find even for a designated fault tolerance mechanism, some small change in structure can lead to dramatic changes in the efforts. These findings have implications for practical industrial production.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

The Future of Test -- Product Integration and its Impact on Test 测试的未来——产品集成及其对测试的影响

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.67

Michael Campbell

{"title":"The Future of Test -- Product Integration and its Impact on Test","authors":"Michael Campbell","doi":"10.1109/DFT.2009.67","DOIUrl":"https://doi.org/10.1109/DFT.2009.67","url":null,"abstract":"Driving leading edge products with high quality while designs, flows, and processes advance with Moore’s Law will require the semiconductor industry to continue to drive for increasing innovative DFT strategies. The test industry will need to drive for new ideas in the areas of: yield analysis, modeling, test techniques, and defect / fault tolerance. To continue cost effective products while costs escalate, yield analysis will need to take far greater consideration of advanced statistical techniques including consideration of spatial randomness. As UDSM processes become more sensitive to variations in lithography, random particle defects, overlay errors, and printability, it is inevitable that new methods will need to be developed to address the economics of Moore’s Law. At the same time, this convergence will put more demand on design/ circuit techniques as well as the need for advanced yield and process control techniques. IP integration drives intersection of dissimilar IP (EG: low power, high speed, RF, etc) requirements where the need for fault tolerant design will be required to achieve HVM. The key area for new DFT development is analog like methods to accommodate defect tolerance will be required HSIO, integrated RF cores, as well as the introduction of non-conventional fabrication methods are required to meet cost, quality and reliability demands.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122204979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of Resistive Open Defects in a Synchronizer 同步器电阻性开路缺陷分析

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.34

Hyoung-Kook Kim, W. Jone, Laung-Terng Wang

引用次数: 4

An Incremental Approach to Functional Diagnosis 一种功能诊断的增量方法

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.29

Luca Amati, C. Bolchini, L. Frigerio, F. Salice, B. Eklow, Arnold Suvatne, E. Brambilla, F. Franzoso, Michele Martin

引用次数: 22

Software-Based Hardware Fault Tolerance for Many-Core Architectures 基于软件的多核架构硬件容错

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.36

H. Wunderlich

引用次数: 0

Testing of Switch Blocks in Three-Dimensional FPGA 三维FPGA中开关模块的测试

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.26

Takumi Hoshi, K. Namba, Hideo Ito

引用次数: 2

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level 在寄存器传输级统一功率效率和故障检测的ILP公式

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.19

Yu Liu, Kaijie Wu

引用次数: 3

On the Functional Qualification of a Platform Model 论平台模型的功能定性

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.15

G. D. Guglielmo, F. Fummi, G. Pravadelli, M. Hampton, Florian Letombe

{"title":"On the Functional Qualification of a Platform Model","authors":"G. D. Guglielmo, F. Fummi, G. Pravadelli, M. Hampton, Florian Letombe","doi":"10.1109/DFT.2009.15","DOIUrl":"https://doi.org/10.1109/DFT.2009.15","url":null,"abstract":"This work focuses on the use of functional qualification for measuring the quality of co-verification environments for hardware/software (HW/SW) platform models. Modeling and verifying complex embedded platforms requires co-simulating one or more CPUs running embedded applications on top of an operating system, and connected to some hardware devices. The paper describes first a HW/SW co-simulation framework which supports all mechanisms used by software, in particular by device drivers, to access hardware devices so that the target CPU’s machine code can be simulated. In particular, synchronization between hardware and software is performed by the co-simulation framework and, therefore, no adaptation is required in device drivers and hardware models to handle synchronization messages. Then, CertitudeTM, a flexible functional qualification tool, is introduced. Functional qualification is based on the theory of mutation analysis, but it is extended by considering a mutation to be killed only if a testcase fails. Certitude(TM) automatically inserts mutants into the HW/SW models and determines if the verification environment can detect these mutations. A known mutant that cannot be detected points to a verification weakness. If a mutant cannot be detected, there is evidence that actual design errors would also not be detected by the co-verification environment. This is an iterative process and functional qualification solution provides the verifier with information to improve the co-verification environment quality. The proposed approach has been successfully applied on an industrial platform as shown in the experimental result section.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130184956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments 通过刺激碎片的水平/垂直移动提高xor减压器的有效性

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI: 10.1109/DFT.2009.9

N. Alawadhi, O. Sinanoglu

{"title":"Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments","authors":"N. Alawadhi, O. Sinanoglu","doi":"10.1109/DFT.2009.9","DOIUrl":"https://doi.org/10.1109/DFT.2009.9","url":null,"abstract":"While test stimulus compression helps reduce test time and data volume, and thus alleviates test costs, the delivery of certain test vectors may not be possible, leading to test quality degradation. Whether a test vector is encodable in the presence of a decompressor strongly hinges on the distribution of its care bits. Utilization of stimulus manipulation techniques improves test pattern encodability as the distribution of care bits can be judiciously controlled. The desired test vector is delivered by resolving the stimulus conflicts that would have otherwise lead to pattern unencodability. Stimulus manipulation in the form of horizontal move of stimulus fragments has been shown to improve fan-out decompressors. In this work, we propose manipulation techniques in the form of horizontal or vertical move of stimulus fragments in order to improve XOR-based decompressors. Improvement in test pattern encodability reflects into savings in test costs and/or increase in test quality. The hardware and algorithmic support for each solution are also elaborated on, demonstrating the practicality of the proposed manipulation techniques.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127174731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3