{"title":"A probabilistically analysable cache implementation on FPGA","authors":"Hassan Anwar, Chao-Wu Chen, G. Beltrame","doi":"10.1109/NEWCAS.2015.7181984","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181984","url":null,"abstract":"Predicting the timing behaviour of modern computer architectures can be extremely difficult. Probabilistic Timing Analysis (PTA) is a recent technique to compute the execution time of a program within a given confidence interval, but requires specially designed hardware with certain properties. This work addresses the implementation of a probabilistically analyzable L1 instruction and data cache for the Ion MIPS32 processor on FPGA. We developed a random placement and replacement policy that fulfills all the requirements for PTA. Our experiments show that the cache fulfills all the requirements for PTA, and program timing can be determined with arbitrary accuracy. In addition, random placement and replacement improve the observed worst case execution time (WCET) from 6% to 19% w.r.t. a Least Recently Used policy.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123891304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parinaz Hadadtehrani, Pouya Kamalinejad, Reza Molavi, S. Mirabbasi
{"title":"An adaptive magnetically coupled wireless power transmission system","authors":"Parinaz Hadadtehrani, Pouya Kamalinejad, Reza Molavi, S. Mirabbasi","doi":"10.1109/NEWCAS.2015.7181982","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181982","url":null,"abstract":"An adaptive control mechanism to improve the efficiency of magnetically coupled resonators (MCRs) used in wireless power transmission is presented. To minimize the degradation in power transfer efficiency, the proposed system dynamically adjusts the capacitance of MCRs as the distance between the transmitter (TX) and receiver (RX) coils changes. The control unit operates in a self-sufficient manner through rectifying a portion of the AC signal present on TX and RX coils. A proof-of-concept circuit operating at 13.56 MHz is designed in a 0.13 μm CMOS technology and simulation results confirm the validity of the proposed scheme.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121165380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization of spectral resources allocation in a context of RF network on chip","authors":"Lounis Zerioul, M. Ariaudo, E. Bourdel","doi":"10.1109/NEWCAS.2015.7182105","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182105","url":null,"abstract":"The radio frequency network on chip (RFNoC) is proposed as a solution to the network on chip issue. The maximizing of the number of the communication paths is required to increase the aggregate throughput. According to the configuration of the RFNoC and the organization of the repartition of the available spectral resources, the quality of the signal may be influenced. An analysis of the effect of the repartition of the spectral resources on the signal to interference plus noise ratio of the signal exchanged in the radio frequency network on chip is described in the content of this paper, where the final purpose is the optimizing of the overall throughput. When the signal to interference plus noise ratio is significantly deteriorated, some solutions are proposed to improve the quality of the transmissions.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124502279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tunnel FET device characteristics for RF energy harvesting passive rectifiers","authors":"David Cavalheiro, F. Moll, S. Valtchev","doi":"10.1109/NEWCAS.2015.7182102","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182102","url":null,"abstract":"The lack of high power conversion efficiency in RF passive rectifier circuits at sub-μW power levels with current MOSFET technologies is directly related with the difficulty of the transistors in conducting the required level of current at low voltage values. With a different carrier injection mechanism, the superior electrical characteristics of the Tunnel FET devices at low voltage values (sub-0.25 V) can outperform the process of energy conversion at ultra-low power, thus improving the operation range of RF energy harvesting circuits. In this work, a simulation study on the doping profile and material selection of Tunnel FET devices shows the impact of device properties in rectifier circuit efficiency.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123349012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded instruments for enhancing dependability of analogue and mixed-signal IPs","authors":"J. Wan, H. Kerkhoff","doi":"10.1109/NEWCAS.2015.7181979","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181979","url":null,"abstract":"The idea of an embedded instrument (EI) is to embed some form of test and measurement into silicon to characterize, debug and test chips. The concept of the EI is different from build-in self test (BIST) and other kinds of monitors by the fact that embedded instruments can provide the user with rich and detailed information with respect to the performances of the target, not just a true/false indication. In this paper, two embedded instruments for analogue and mixed-signal IPs focusing on dependability applications are introduced. They are the EI for measuring MOS transistors' threshold voltage and the EI for testing OpAmps' gain and offset. Measurements as well as simulation results are provided to validate these EIs and show their efficiency in monitoring the ageing of analogue and mixed-signal IPs in their life time, and enable the path to enhance dependability.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Subbiah, N.A. Elneel, G. Varga, A. Ashok, D. Schroeder
{"title":"Low power on-chip load tracking-zero compensation method for low dropout regulator","authors":"I. Subbiah, N.A. Elneel, G. Varga, A. Ashok, D. Schroeder","doi":"10.1109/NEWCAS.2015.7182099","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182099","url":null,"abstract":"This paper describes a novel frequency compensation method for a low dropout regulator (LDO). The proposed load tracking-zero compensation circuit not only eliminates the need for a bulky external off-chip capacitor that is typically employed in conventional compensation techniques, but also consumes very low additional quiescent current of 7.5μA that makes this method highly suitable for integrated SoC power management applications. It is demonstrated that this compensation technique, designed for the LDO in 130-nm CMOS technology, improves the stability and enhances the load regulation of the low dropout regulator.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114813860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cycle-slipping pull-in range of bang-bang PLLs","authors":"Amer Samarah, A. C. Carusone","doi":"10.1109/NEWCAS.2015.7182020","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182020","url":null,"abstract":"An analysis of the cycle slipping behavior of a bang-bang phase locked loop (PLL) far from its lock provides expressions for the pull-in frequency range. Behavioral simulation is used to validate the analytical results which estimate the pull-in range at least 40% more accurately than prior work.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114720989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.6V-supply bandgap reference in 65 nm CMOS","authors":"Omar Abdelfattah, I. Shih, G. Roberts, Y. Shih","doi":"10.1109/NEWCAS.2015.7182023","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182023","url":null,"abstract":"A bandgap voltage reference that operates from a power supply of 0.6 V is presented in this paper. The circuit is based on an all-CMOS implementation that allows operation below the base-emitter voltage limit by eliminating parasitic vertical bipolar-junction-transistors. Low-voltage design techniques are deployed to design an op-amp that can obviate the need for a start-up circuit. The design was implemented in 65 nm CMOS technology. The measured reference voltage is 275 mV with an average temperature coefficient of 176 ppm/°C from -50°C to 80°C without trimming. The circuit consumes 62 μW of power and occupies 0.011 mm2 of chip area.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127626375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal
{"title":"Sub-picoampere, 7-decade current to frequency converter for current sensing","authors":"E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal","doi":"10.1109/NEWCAS.2015.7182071","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182071","url":null,"abstract":"An Application Specific Integrated Circuit (ASIC) has been designed in order to demonstrate the limitations and the challenges in ultralow current sensing. The Utopia (Ultralow Picoammeter) ASIC is foreseen to be the front-end in the new radiation measurement system for personnel safety at CERN. It is based on the topology of a Current to Frequency Converter (CFC) and has a wide dynamic range of 7 decades without range changing. Four different channels have been implemented in order to evaluate the limits regarding sub-picoampere current measurements. Test currents starting from -50 fA have been measured.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Roma, J. Bosch, M. Carmona, A. Casas, A. Herms, José María Gómez Hidalgo, Manel López, J. Sabater, J. Baumgartner, T. Maue, E. Nakai, Wolfang Schmidt, R. Volkmer
{"title":"A space grade camera for image correlation","authors":"D. Roma, J. Bosch, M. Carmona, A. Casas, A. Herms, José María Gómez Hidalgo, Manel López, J. Sabater, J. Baumgartner, T. Maue, E. Nakai, Wolfang Schmidt, R. Volkmer","doi":"10.1109/NEWCAS.2015.7182110","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182110","url":null,"abstract":"In this paper we describe the space grade camera we developed for the Polarimetric and Helioseismic Imager (PHI) instrument of the Solar Orbiter (SO) mission. The camera, called Correlation Tracking Camera (CTC) will be part of the Image Stabilization System (ISS) used to compensate the spacecraft jitter. Since the ISS works on a correlator basis, the CTC requires a high frame rate while keeping the power consumption as low as possible. The CTC works at a nominal frame rate of 414 fps for 128 pixels square images with a latency below the microsecond. The images have a 10 bit resolution and the tests shows an effective number of bits (ENOB) above 9.3. Also, the full ISS closed-loop has been successfully tested with this camera.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125783922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}