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2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)最新文献

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Low-power 3rd order ΣΔ modulator in CMOS 90-nm for sensor interface applications 低功耗三阶ΣΔ调制器在CMOS 90纳米传感器接口应用
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-08-10 DOI: 10.1109/NEWCAS.2015.7182044
Luca Giuffredi, G. Pietrini, M. Ronchi, A. Magnanini, A. Boni
{"title":"Low-power 3rd order ΣΔ modulator in CMOS 90-nm for sensor interface applications","authors":"Luca Giuffredi, G. Pietrini, M. Ronchi, A. Magnanini, A. Boni","doi":"10.1109/NEWCAS.2015.7182044","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182044","url":null,"abstract":"The manuscript describes the design and implementation of a low-power, fully differential switched-capacitor ΣΔ modulator in STM 90-nm CMOS technology, for sensor interface applications. With the aid of an accurate behavioral model, the power consumption is minimized without sacrificing the effective resolution. Through the optimization of single-stage integrators, with feed-forward summation, and using a class-A OTA op-amp with local positive feedback, a total power consumption of 50-μW from a 1.2-V power supply is achieved. The modulator reaches a peak SNR of 94-dB and a noise floor of 8.6-μV-rms over a 250-Hz signal bandwidth. The proposed design is one of the first modulator implemented in a 90-nm CMOS and achieving a 16-bit effective resolution with a 1.5-pJ/conv. figure-of-merit.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115210806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra-wideband voltage controlled oscillator with commutable phases for BPSK implementation 用于BPSK实现的具有可交换相位的超宽带电压控制振荡器
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-08-10 DOI: 10.1109/NEWCAS.2015.7182048
R. Vauché, E. Muhr, N. Tall, Abderrahmane Haloua, S. Bourdel, J. Gaubert, N. Dehaese, H. Barthélemy
{"title":"Ultra-wideband voltage controlled oscillator with commutable phases for BPSK implementation","authors":"R. Vauché, E. Muhr, N. Tall, Abderrahmane Haloua, S. Bourdel, J. Gaubert, N. Dehaese, H. Barthélemy","doi":"10.1109/NEWCAS.2015.7182048","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182048","url":null,"abstract":"An ultra-wideband Voltage Controlled Oscillator (VCO) is presented in this paper. The circuit achieves fast startups and stops which allow wideband pulses to be generated. In addition, the VCO allows bipolar modulations as Binary Phase Shift Keying to be implemented without the need of a shaping circuit as a mixer. The proposed VCO has been integrated on a silicon area of 0.003mm2 in a 65nm CMOS technology operating with a supply voltage of 1.2V. The oscillator output provides large differential oscillations from 2.6GHz to 12.3GHz. Measurement has demonstrated the frequency agility of the proposed VCO which covers the mandatory channels of the low (resp. high) bands centered on 4492.8MHz (resp. 7987.2MHz) defined by the IEEE 802.15.4 standard. The VCO power consumption is about 3.2mW/GHz. By using Current Mode Logic (CML) gates, the power consumption can be reduced to 3.84uW only when the VCO is not running (switch off).","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125646275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low complexity fast filter bank-based channelization in L-DACS1 for aeronautical communications 航空通信L-DACS1中基于滤波器组的低复杂度快速信道化
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-08-10 DOI: 10.1109/NEWCAS.2015.7181995
S. Dhabu, A. P. Vinod, A. Madhukumar
{"title":"Low complexity fast filter bank-based channelization in L-DACS1 for aeronautical communications","authors":"S. Dhabu, A. P. Vinod, A. Madhukumar","doi":"10.1109/NEWCAS.2015.7181995","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181995","url":null,"abstract":"Studies related to the growth of air traffic forecast that the air traffic is likely to double in next decade, which will heavily increase the load on aeronautical communications. Current systems will not be able to support this increase in the aeronautical communications; and hence there is a need of new reliable and high speed communication system for the air-to-ground (A/G) communications. European Organization for the Safety of Air Navigation (EUROCONTROL) has proposed the use of IEEE L-band for A/G communications. Currently, two candidate systems are being studied for this proposed L-band Digital Aeronautical Communications System (L-DACS), namely L-DACS1 and LDACS2, under the initiatives funded by EUROCONTROL. In this paper we consider one of the candidate systems, L-DACS1, and propose a fast filter bank (FFB)-based channelizer for L-DACS1. We show that use of FFB enables simultaneous extraction of up to eight L-DACS1 channels (frequency bands), with 49% to 85% savings in number of multipliers over conventional methods and faster filtering operation without compromising on the filtering performance.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133898071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Integrated differential high-voltage transmitting circuit for CMUTs cmut的集成差分高压发射电路
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182038
Pere Llimós Muntal, D. Larsen, Kjartan Færch, I. Jørgensen, E. Bruun
{"title":"Integrated differential high-voltage transmitting circuit for CMUTs","authors":"Pere Llimós Muntal, D. Larsen, Kjartan Færch, I. Jørgensen, E. Bruun","doi":"10.1109/NEWCAS.2015.7182038","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182038","url":null,"abstract":"In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption at the scanner operation conditions is 0.754mW without the transducer load and 0.936mW with it.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A black-box approach to RF LNA design RF LNA设计的黑盒方法
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182080
Michele Spasaro, F. Alimenti, D. Zito
{"title":"A black-box approach to RF LNA design","authors":"Michele Spasaro, F. Alimenti, D. Zito","doi":"10.1109/NEWCAS.2015.7182080","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182080","url":null,"abstract":"This paper presents a novel power-constrained algorithmic design methodology for radiofrequency (RF) low-noise amplifiers (LNAs). The methodology is based on matrix descriptions of the transistors allowing for the first time the derivation of exact synthesis equations for input impedance matching and transducer gain optimization. The equations are embedded in an algorithm for design tradeoffs between noise performance and gain. In particular, the synthesis equations are demonstrated for the cascode topology with inductive degeneration. The matrices required by the mathematical description are derived through simulations, allowing the algorithmic design methodology to be accurate, flexible (i.e. applicable to any two-port active device), and compliant with the needs of intellectual property protection since no dc, small-signal, or noise model parameters are required. The methodology is validated through the design of a 2 mW 2.45 GHz LNA in a predictive 90 nm CMOS technology.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127378600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Zero-power mismatch-independent Digital to Analog converter 零功率不匹配独立的数模转换器
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182106
Ata Khorami, M. Sendi, Ali Nikoofard, M. Sharifkhani
{"title":"Zero-power mismatch-independent Digital to Analog converter","authors":"Ata Khorami, M. Sendi, Ali Nikoofard, M. Sharifkhani","doi":"10.1109/NEWCAS.2015.7182106","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182106","url":null,"abstract":"A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Single-carrier frequency division multiple access with Discrete Cosine Transform Type-I 离散余弦变换型单载波频分多址
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182111
F. Cruz-Roldán, Freddy A. Pinto-Benel, M. Jiménez, G. Vidal
{"title":"Single-carrier frequency division multiple access with Discrete Cosine Transform Type-I","authors":"F. Cruz-Roldán, Freddy A. Pinto-Benel, M. Jiménez, G. Vidal","doi":"10.1109/NEWCAS.2015.7182111","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182111","url":null,"abstract":"We present a novel single-carrier frequency division multiple access transceiver based on Discrete Cosine Transform Type-I (DCT1). We show the kind of redundancy (as prefix and suffix) that must be appended into each data symbol to be transmitted, and also the symmetry to be imposed on the channel impulse response, so that the channel matrix is diagonalized. Moreover, we show how the channel equalization can be carried out by means of a bank of scalars obtained through the DCT1 of a filter-right-half derived from the symmetric channel impulse response. This study is completed with several computer simulations.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
0.7-V bulk-driven three-stage class-AB OTA 0.7 v体积驱动三级ab级OTA
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182069
Elena Cabrera-Bernal, S. Pennisi, A. D. Grasso
{"title":"0.7-V bulk-driven three-stage class-AB OTA","authors":"Elena Cabrera-Bernal, S. Pennisi, A. D. Grasso","doi":"10.1109/NEWCAS.2015.7182069","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182069","url":null,"abstract":"A high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution exploits a three-gain-stage topology and, as a distinctive behavior, provides an inherent class-AB performance with simple and robust standby current control. A 0.7-V supply OTA is designed using a 180-nm standard CMOS technology. Post layout simulations show a 61-dB open loop gain and a unity gain bandwidth of 3.6 MHz, under a capacitive load of 20 pF. Significant performance improvement when compared to prior art is achieved, so that the best figure of merit is found.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126918801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors 用高效加法器压缩器增强HEVC插值滤波器硬件架构
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182087
C. Diniz, M. Fonseca, E. Costa, S. Bampi
{"title":"Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors","authors":"C. Diniz, M. Fonseca, E. Costa, S. Bampi","doi":"10.1109/NEWCAS.2015.7182087","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182087","url":null,"abstract":"The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are area- and power-efficient operators that are applied when intermediate additions are not required, which is the case for interpolation filters. This work employs various hierarchical adder compressor structures in the interpolation filter datapaths of a state-of-the-art HEVC interpolation filter architecture. Hardware design results show that datapaths using adder compressors reduce power by up to 15% and power delay product by up to 30% compared to the same filters with ripple-carry adders.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115080790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of small antenna on linear power amplifier performance in a co-design approach 协同设计方法下小天线对线性功率放大器性能的影响
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7181998
E. Abdallah, A. Giry, S. Bories, D. Nicolas, C. Delaveaud
{"title":"Impact of small antenna on linear power amplifier performance in a co-design approach","authors":"E. Abdallah, A. Giry, S. Bories, D. Nicolas, C. Delaveaud","doi":"10.1109/NEWCAS.2015.7181998","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181998","url":null,"abstract":"The main objective of this study is to determine the impact of a co-designed small antenna on linear power amplifier (PA) performances. Special attention is paid to load-pull optimization to derive suitable values of the antenna input impedance at the operating frequency and the first higher-order harmonics. The impact of the antenna impedance profile in the operational band on PA performance is also addressed. It is found that the PA is more linear, when its operating frequency is below the antenna resonance, compared to other configurations. A microstrip patch antenna which provide the optimal impedance is developed and results demonstrate the benefits of the co-design approach with new antenna.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116035865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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