2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)最新文献_第2页

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic 一种4×4-bit倍频LSI实现的两相时钟亚阈值绝热逻辑

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182098

Kazunari Kato, Yasuhiro Takahashi, T. Sekine

引用次数: 4

Cloud-based orthognathic surgical planning platform 基于云的正颌手术计划平台

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182051

W. Swinkels, Yi Sun, Bart Stukken, C. Politis, L. Claesen

引用次数: 1

Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI CMOS VLSI中面积和高能效FIR滤波器的近似加法器合成

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182095

L. Soares, S. Bampi, E. Costa

{"title":"Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI","authors":"L. Soares, S. Bampi, E. Costa","doi":"10.1109/NEWCAS.2015.7182095","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182095","url":null,"abstract":"This paper proposes the synthesis of approximate adders to improve the area and energy efficiency of FIR filters implemented in CMOS. We demonstrate energy per sample savings and hardware area reduction in the filters with our design method. All savings are in addition to the improvements obtained on previously optimized digital filters in which state-of-the-art multiplierless multiple constant multiplication optimizations are included in the design method. Digital finite impulse response filters are largely used in multimedia systems which can tolerate levels of approximations in computing or loss of accuracy in the arithmetic dataflow. Our work deals with different levels of approximation in ripple-carry adders which are part of the filters implemented in hardware, fully synthesized in CMOS, and later compared to the best precise implementation of the same filter. Our results show that the effort to explore area and energy savings in low power optimized circuits through the approximate computing approach is validated with area and energy reductions up to 18.8% and 15.5% respectively, without compromising the filters frequency response or the Signal to Noise Ratio (SNR) of recorded 16-bit audio signals. Our approximate adder method enables a higher degree of area and energy efficiencies in CMOS VLSI filters.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Optimized operation and temperature dependence of a direct light-to-time converter 直接光-时间转换器的优化操作和温度依赖性

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182009

D. Sallin, A. Koukab, M. Kayal

引用次数: 1

Efficiency enhancement using adaptive bias control for 60GHz power amplifier 利用自适应偏置控制提高60GHz功率放大器的效率

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182050

A. Serhan, E. Lauga-Larroze, J. Fournier

{"title":"Efficiency enhancement using adaptive bias control for 60GHz power amplifier","authors":"A. Serhan, E. Lauga-Larroze, J. Fournier","doi":"10.1109/NEWCAS.2015.7182050","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182050","url":null,"abstract":"A single-stage 60GHz class-A bipolar power amplifier (PA) is fabricated in a BiCMOS 55nm technology. In order to enhance the power added efficiency (PAE) behavior of the PA, a bias control loop, based on direct power detection, is implemented in order to dynamically adjust the DC bias current of the PA according to its output power level. A power detector (PD) is connected directly at the output of the amplifier in order to track the envelope variation of its output signal. The employed PD has a dynamic range of more than 30dB, and a maximum power consumption of 0.8mW. Under constant bias conditions, the PA has a power gain of around 7dB, a maximum PAE of 16%, and an output compression point of around 7.5dBm while driving 25.8mA under 1.2V supply voltage. Under adaptive bias control, the mean value of the DC current is reduced down to 20.8mA, while maintaining high power gain, leading to a significant enhancement of the PAE over the linear input dynamic range of the PA. System level simulations show that the applied technique enhances the average PAE and DC power consumption by 18% without significant discrepancies on the EVM, ACPR, and power gain.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"573 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127752122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

SystemC AMS modeling of a sensor node energy consumption and battery state-of-charge for WSN WSN传感器节点能量消耗和电池充电状态的SystemC AMS建模

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7181996

M. Vasilevski, E. Queiroz, A. L. Fonseca, I. Silva, S. Catunda, L. A. Guedes

引用次数: 7

A power-efficient 14-bit 250MS/s pipelined ADC 一个高效的14位250MS/s流水线ADC

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182042

Weitao Li, Fule Li, Ya Wang, Shengjing Li, Chun Zhang, Zhihua Wang

引用次数: 3

A switched-capacitor controlled digital-current modulated class-E EER transmitter 一种开关电容控制的数字电流调制e类变送器

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182014

Wen Yuan, J. Walling

引用次数: 3

Low voltage CMOS charge pump with excellent current matching based on a rail-to-rail current conveyor 基于轨对轨电流输送的电流匹配良好的低压CMOS电荷泵

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182077

K. Moustakas, S. Siskos

{"title":"Low voltage CMOS charge pump with excellent current matching based on a rail-to-rail current conveyor","authors":"K. Moustakas, S. Siskos","doi":"10.1109/NEWCAS.2015.7182077","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182077","url":null,"abstract":"A low voltage charge pump with excellent current matching in a wide dynamic range is proposed. It is aimed to be used in state of the art frequency synthesizers. The key concept is the direct equation of currents, instead of indirectly equating transistor voltages, using the current following action of a second generation current conveyor. The voltage buffer of the current conveyor is used to replicate the operating conditions of the NMOS current sink and create an equal current at the X input. According to the PFD signals this current can be mirrored to the Z output and be used to source current to the charge pump output, while a source switching scheme is used to reduce glitches. The proposed design exhibits both static and dynamic high performance characteristics in terms of very low DC current mismatch, of the order of 0,05%, and suppressed transient glitches. Both these non-idealities degrade performance of PLLs inducing reference spurs and phase offset, and thus must be minimized. The proposed circuit is implemented in TSMC 65nm process and simulation results demonstrate performance in a wide output voltage range from 100mV to 950mV.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117319458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

81–86 GHz VCO for Backhaul application with S-CPS based differential inductor in BiCMOS 55nm technology 基于S-CPS的差动电感BiCMOS 55nm技术，用于回程应用的81-86 GHz压控振荡器

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182033

Ekta Sharma, Alfredo Bautista, E. Pistono, P. Ferrari, S. Bourdel

引用次数: 2