A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic

In this paper, we describe an LSI implementation and the measurement results of a 4×4-bit multiplier which has an ultra-low power dissipation characteristic. The proposed multiplier uses an ultra-low power technique which combines adiabatic logic and a subthreshold circuit. The output functionality and power consumption of the fabricated LSI chip at a 1 kHz frequency and 0.6 V peak voltage operation are measured and compared with conventional static CMOS and subthreshold static CMOS.