Low-power 3rd order ΣΔ modulator in CMOS 90-nm for sensor interface applications

Abstract

The manuscript describes the design and implementation of a low-power, fully differential switched-capacitor ΣΔ modulator in STM 90-nm CMOS technology, for sensor interface applications. With the aid of an accurate behavioral model, the power consumption is minimized without sacrificing the effective resolution. Through the optimization of single-stage integrators, with feed-forward summation, and using a class-A OTA op-amp with local positive feedback, a total power consumption of 50-μW from a 1.2-V power supply is achieved. The modulator reaches a peak SNR of 94-dB and a noise floor of 8.6-μV-rms over a 250-Hz signal bandwidth. The proposed design is one of the first modulator implemented in a 90-nm CMOS and achieving a 16-bit effective resolution with a 1.5-pJ/conv. figure-of-merit.