2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)最新文献

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Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB 自适应IEEE 802.15.4 DBB闭环控制器的设计与实现
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7181989
V. Lenoir, W. Lombardi, D. Lattard, A. Jerraya
{"title":"Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB","authors":"V. Lenoir, W. Lombardi, D. Lattard, A. Jerraya","doi":"10.1109/NEWCAS.2015.7181989","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181989","url":null,"abstract":"The high demand of low-power radio transceivers for the Internet of Things drives the design of innovative wireless architectures. In this context, the energy efficiency problem arises from the strong variability of the radio channel. As a solution, we propose to dynamically optimize the receiver performance jointly with the power consumption, in order to reach a low-margin operating mode. For this purpose, we have developed an IEEE 802.15.4 Digital Baseband (DBB) with a built-in tunable subsampling mechanism. This paper describes the design and the hardware implementation of a low-complexity controller for managing this adaptive system. It explains the basic methodology and points out some practical considerations for a robust and efficient implementation. As a result, the paper shows the impact of the controller design on the baseband power consumption.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI 高速可配置带宽时交错数字δ - σ调制器和28nm UTBB FDSOI合成的考虑
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182049
Răzvan-Cristian Marin, A. Frappé, A. Kaiser, A. Cathelin
{"title":"Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI","authors":"Răzvan-Cristian Marin, A. Frappé, A. Kaiser, A. Cathelin","doi":"10.1109/NEWCAS.2015.7182049","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182049","url":null,"abstract":"This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132020129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A high PSRR, ultra-low power 1.2V curvature corrected Bandgap reference for wearable EEG application 高PSRR,超低功耗1.2V曲率校正带隙参考可穿戴EEG应用
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182036
M. U. Abbasi, George Raikos, Ruchir Saraswat, E. Rodríguez-Villegas
{"title":"A high PSRR, ultra-low power 1.2V curvature corrected Bandgap reference for wearable EEG application","authors":"M. U. Abbasi, George Raikos, Ruchir Saraswat, E. Rodríguez-Villegas","doi":"10.1109/NEWCAS.2015.7182036","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182036","url":null,"abstract":"A high PSRR, ultra-low power 1.2V voltage supply (VDD) curvature corrected Bandgap reference for Wearable EEG application is described in this paper. The proposed bandgap reference can operate with supply as low as 1V, and provides a supply regulation of 0.113%/V with VDD range of 1.01-2.62V. Piecewise curvature compensation is employed to reduce the temperature coefficient (TC) of bandgap reference from 22.84ppm /°C to 2.295ppm/°C, with a temperature range -10~110°C. The bandgap reference circuit was designed in standard 0.18um CMOS technology where a proportional to absolute temperature (PTAT) and a complementary to absolute temperature (CTAT) current generation circuit were used to generate first order bandgap reference. A non-linear current was generated using PTAT current and CTAT voltage generation circuit and a power supply rejection ratio (PSRR) of 84.62dB (at DC) was achieved to reduce the interference from power supply noise, in order to meet the specifications for wearable wireless EEG sensing systems. The total current consumption of the whole bandgap reference including biasing and startup circuit is only 4.691uA which fits the requirement of battery powered wearable wireless sensing applications.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131556089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Additive companding implementation to reduce ADC constraints for multiple signals digitization 加性压缩实现减少多信号数字化的ADC约束
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182017
Mathieu Vallerian, F. Hutu, B. Miscopein, G. Villemaud, T. Risset
{"title":"Additive companding implementation to reduce ADC constraints for multiple signals digitization","authors":"Mathieu Vallerian, F. Hutu, B. Miscopein, G. Villemaud, T. Risset","doi":"10.1109/NEWCAS.2015.7182017","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182017","url":null,"abstract":"In urban sensor networks, the diversity of propagation conditions can lead to the simultaneous reception of signals having very different power levels. Given the diversity of wireless technologies used in this area, implementing gateways using a Software-Defined Radio (SDR) approach seems to be a very practical solution. Overcoming the large dynamic range may however require a very high resolution Analog-to-Digital Converter (ADC) to digitize the weakest signal with a satisfying precision. One possibility to relax this requirement is to use a companding technique before digitization. This paper describes how to use an additive companding approach to reduce ADC's complexity and proposes two implementations of the compressing law.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133279161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 30MHz 28dBm-IIP3 3.2mW fully-differential Sallen-Key 4th-order filter with out-of-band zeros cancellation 30MHz 28dBm-IIP3 3.2mW带外零抵消全差分萨伦键四阶滤波器
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182066
F. Resta, M. Matteis, A. Pezzotta, S. D’Amico, A. Baschirotto
{"title":"A 30MHz 28dBm-IIP3 3.2mW fully-differential Sallen-Key 4th-order filter with out-of-band zeros cancellation","authors":"F. Resta, M. Matteis, A. Pezzotta, S. D’Amico, A. Baschirotto","doi":"10.1109/NEWCAS.2015.7182066","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182066","url":null,"abstract":"In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18μm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197μVRMS.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120907379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synchronous Electric Charge Extraction for multiple piezoelectric energy harvesters 多压电能量采集器的同步电荷提取
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182103
S. Boisseau, P. Gasnier, Matthias Perez, C. Bouvard, M. Geisler, A. Duret, G. Despesse, J. Willemin
{"title":"Synchronous Electric Charge Extraction for multiple piezoelectric energy harvesters","authors":"S. Boisseau, P. Gasnier, Matthias Perez, C. Bouvard, M. Geisler, A. Duret, G. Despesse, J. Willemin","doi":"10.1109/NEWCAS.2015.7182103","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182103","url":null,"abstract":"This paper presents a power management circuit implementing a Synchronous Electric Charge Extraction on piezoelectric energy harvesters based on a flyback architecture. The novelty of this circuit lies in its ability to handle multiple energy harvesters operating at different frequencies and different output voltages with a single and standard flyback coupled inductor. The power harvested by the various scavengers is stored in a single and mutual storage capacitor. By construction, the power management circuit is capable of dealing with high input voltages (>100V). Its power consumption is about 1.15μA@3V per energy harvester and its conversion efficiency reaches 83%; its good operation has been validated by simulations and experiments on two vibration energy harvesters.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116115472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Approximate computing with unreliable dynamic memories 不可靠动态存储器的近似计算
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182027
Shrikanth Ganapathy, A. Teman, R. Giterman, A. Burg, G. Karakonstantis
{"title":"Approximate computing with unreliable dynamic memories","authors":"Shrikanth Ganapathy, A. Teman, R. Giterman, A. Burg, G. Karakonstantis","doi":"10.1109/NEWCAS.2015.7182027","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182027","url":null,"abstract":"Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide higher density and/or reduced power consumption. One major challenge that impedes the widespread adoption of eDRAM is that they require frequent refreshes potentially reducing the availability of the memory in periods of high activity and also consuming significant amount of power due to such frequent refreshes. Reducing the refresh rate while on one hand can reduce the power overhead, if not performed in a timely manner, can cause some cells to lose their content potentially resulting in memory errors. In this paper, we consider extending the refresh period of gain-cell based dynamic memories beyond the worst-case point of failure, assuming that the resulting errors can be tolerated when the use-cases are in the domain of inherently error-resilient applications. For example, we observe that for various data mining applications, a large number of memory failures can be accepted with tolerable imprecision in output quality. In particular, our results indicate that by allowing as many as 177 errors in a 16 kB memory, the maximum loss in output quality is 11%. We use this failure limit to study the impact of relaxing reliability constraints on memory availability and retention power for different technologies.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter 半数字FIR DAC用于低功耗单载波IEEE 802.11ad 60GHz发射机
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182016
F. Gebreyohannes, A. Frappé, A. Kaiser
{"title":"Semi-digital FIR DAC for low power single carrier IEEE 802.11ad 60GHz transmitter","authors":"F. Gebreyohannes, A. Frappé, A. Kaiser","doi":"10.1109/NEWCAS.2015.7182016","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182016","url":null,"abstract":"IEEE 802.11ad (WiGig) is an emerging multi-Gb/s wireless standard in the unlicensed 60GHz spectrum. This work presents system level validation of a Single Carrier (SC), QPSK modulated WiGig transmitter based on a semi-digital Finite Impulse Response (FIR) Digital-to-Analog Converter (DAC). The 1.76GS/s complex baseband input signal is upsampled by two to a clock frequency of 3.52GHz. In order to introduce channel shaping and meet the standard requirements, the structure implements a 16th-order direct-form Root-Raised Cosine (RRC) FIR filter. Transmit mask and EVM requirements are met with a large margin while allowing a 14% random mismatches on the current sources implementing the FIR DAC coefficients.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128359928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel optical integrate and dump receiver for clocking signals 一种用于时钟信号的新型光集成转储接收机
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182078
R. Polster, J. L. Jiménez, E. Cassan
{"title":"A novel optical integrate and dump receiver for clocking signals","authors":"R. Polster, J. L. Jiménez, E. Cassan","doi":"10.1109/NEWCAS.2015.7182078","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182078","url":null,"abstract":"A novel integrate and dump receiver for clock signals is presented. The integrate and dump topology is known to be power efficient, but depends on a external clock signal. Here, we introduce a topology that auto generates the dump signal and hence can be used as a clock receiver. The proposed architecture is of special interest for clock channels as it accepts short pulses, instead of a 50 % duty cycle clock, as input signal. This allows big power savings by using pulsed lasers for clock generation in place of continuous wave lasers and optical modulators. The proposed receiver includes inherent duty cycle control and outputs, independent of the input, a 50 % duty cycle clock signal. Finally, the proposed topology is compared to classical approaches and is found to be the most power efficient solution in terms of overall optical link power consumption.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128280879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and design of Ka-band SoC radiometer for space detection of solar flares 用于太阳耀斑空间探测的ka波段SoC辐射计的分析与设计
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182070
L. Aluigi, D. Zito
{"title":"Analysis and design of Ka-band SoC radiometer for space detection of solar flares","authors":"L. Aluigi, D. Zito","doi":"10.1109/NEWCAS.2015.7182070","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182070","url":null,"abstract":"This paper presents the results of the feasibility study of a millimeter-wave system-on-chip Dicke radiometer for space-based detection of solar flares, operating at a frequency of 36.8 GHz and expected to be implemented in a 0.25 μm SiGe BiCMOS technology by IHP, under Space evaluations. System analysis and circuit simulations are presented and discussed. The results show a resolution of 0.7 K for an integration time of 0.04 s. These results support the objective targeted with the first implementation of a SoC radiometer for space-based detection of solar flares.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126232491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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