A novel optical integrate and dump receiver for clocking signals

R. Polster, J. L. Jiménez, E. Cassan
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引用次数: 2

Abstract

A novel integrate and dump receiver for clock signals is presented. The integrate and dump topology is known to be power efficient, but depends on a external clock signal. Here, we introduce a topology that auto generates the dump signal and hence can be used as a clock receiver. The proposed architecture is of special interest for clock channels as it accepts short pulses, instead of a 50 % duty cycle clock, as input signal. This allows big power savings by using pulsed lasers for clock generation in place of continuous wave lasers and optical modulators. The proposed receiver includes inherent duty cycle control and outputs, independent of the input, a 50 % duty cycle clock signal. Finally, the proposed topology is compared to classical approaches and is found to be the most power efficient solution in terms of overall optical link power consumption.
一种用于时钟信号的新型光集成转储接收机
提出了一种新颖的时钟信号集成转储接收机。众所周知,集成和转储拓扑是节能的,但依赖于外部时钟信号。在这里,我们介绍一种拓扑结构,它可以自动生成转储信号,因此可以用作时钟接收器。所提出的架构对时钟通道特别感兴趣,因为它接受短脉冲,而不是50%占空比时钟作为输入信号。这允许使用脉冲激光器时钟产生的地方,连续波激光器和光调制器大省电。所提出的接收机包括固有占空比控制和独立于输入的50%占空比时钟信号输出。最后,将所提出的拓扑与经典方法进行比较,发现就整体光链路功耗而言,该拓扑是最节能的解决方案。
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