Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

Abstract

This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.