Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, S. Yuan, Fule Li, Zhihua Wang
{"title":"A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS","authors":"Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, S. Yuan, Fule Li, Zhihua Wang","doi":"10.1109/NEWCAS.2015.7182113","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182113","url":null,"abstract":"This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130605283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Torres, J. Bégueret, Nicolas Martin, D. Belot, T. Taris
{"title":"A novel tunable impedance transmission line for mm-waves applications","authors":"F. Torres, J. Bégueret, Nicolas Martin, D. Belot, T. Taris","doi":"10.1109/NEWCAS.2015.7182035","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182035","url":null,"abstract":"In this paper a novel tunable transmission line operating in V-band (57 GHz to 66 GHz) is presented. Designed in a 130 nm BiCMOS technology, the proposed structure explores ground plane switching to perform impedance tuning. It exhibits a 16 Ohms shift over characteristic impedance - equivalent to 30% of tuning range - with a Q-factor higher than 16 thanks to a shielding used in slow-waves transmission lines. Using this topology versus a classical 50 Ohms coplanar waveguide into a reconfigurable pi-type matching network with tunable stubs, it allows to cover around 100% more of impedances in the Smith Chart with a “2 dimensional” tuning.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CMOS differential neural amplifier with high input impedance","authors":"F. Rummens, S. Renaud, N. Lewis","doi":"10.1109/NEWCAS.2015.7182037","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182037","url":null,"abstract":"We present a CMOS differential neural amplifier with high input impedance, which topology is inspired by the instrumentation amplifier. The miniaturization of the MEAs goes with an increase of the electrodes impedance and necessitates high input impedance neural amplifiers; otherwise it results in a significant loss of signal and low SNR. The circuit presented here is designed on a 0.35 μm CMOS technology. Two versions are described which capacitive input impedance is 1 pF. One is robust to high input offset and consumes 13.5 μA; the other one is more sensitive to offset but consumes only 3.7 μA. Both generate less than 7 μVRMS input-referred noise and their NEF figures are respectively 8.4 and 3.66. These features are competitive in view of the literature on neural amplifiers, while the circuit was specifically designed to present a high input impedance.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130211507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nithin Jose, Nirmal John, Prashuk Jain, P. Raja, T. Prabhakar, K. Vinoy
{"title":"RF powered integrated system for IoT applications","authors":"Nithin Jose, Nirmal John, Prashuk Jain, P. Raja, T. Prabhakar, K. Vinoy","doi":"10.1109/NEWCAS.2015.7182100","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182100","url":null,"abstract":"This work describes an ultra low power three chip system that harvests RF energy for sensing applications. The input RF power levels are typically lower than -6dBm. Our scheme uses two commercially available chips, a DC-DC boost converter and a low power microcontroller. In this paper we present the design of a third chip that compliments these to form a complete system. This chip includes an RF-DC rectifier, low power analog to digital converter (ADC) and a resistor emulation circuit (REC). While the REC helps in enhancing the efficiency of the boost converter, the ADC replaces the one present in the microcontroller and reduces the operating power requirements. The chip is designed in standard 0.18μm CMOS process technology.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132684966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Varga, A. Ashok, I. Subbiah, M. Schrey, S. Heinen
{"title":"A workaround to the higher order derivative issue of threshold voltage based MOSFET models","authors":"G. Varga, A. Ashok, I. Subbiah, M. Schrey, S. Heinen","doi":"10.1109/NEWCAS.2015.7182083","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182083","url":null,"abstract":"Simulation of higher order nonlinear device currents in RF integrated circuits becomes crucial when high linearity is a design goal. Prediction of the nonlinear behavior of passive circuits like mixers, attenuators or switches play an important role in low-distortion designs, but also causes trouble due to the inability of threshold voltage based compact models to inherently model higher order nonlinearities around zero drain-source voltage. This paper introduces a systematic workaround enabling the designer to receive qualitative higher order simulation data around that important operating point when there is no access to one of the advanced surface potential or inversion charge based transistor models.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmed Hamza, S. Ibrahim, M. El-Nozahi, M. Dessouky
{"title":"A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS","authors":"Ahmed Hamza, S. Ibrahim, M. El-Nozahi, M. Dessouky","doi":"10.1109/NEWCAS.2015.7182045","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182045","url":null,"abstract":"This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead of using an array of time amplifiers (TAs) to amplify the time residue, the proposed TDC reduces the power and area consumptions by using only one TA. The designed TDC achieves a resolution of 1.2 ps with a conversion range of 0.614 ns while consuming 0.602 mW at 10 MHz and 8.299 mW at 150 MHz. The achieved figure-of-merit (FoM) of the TDC is 0.108 pJ/conversion at a frequency of 150 MHz.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130994070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware design of a neural processing unit for bio-inspired computing","authors":"Laurent Fiack, Laurent Rodriguez, Benoît Miramond","doi":"10.1109/NEWCAS.2015.7181997","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181997","url":null,"abstract":"Unsupervised artificial neural networks are now considered as a likely alternative to classical computing models in many application domains. For example, recent neural models defined by neuro-scientists exhibit interesting properties for an execution in embedded and autonomous systems: distributed computing, unsupervised learning, self-adaptation, self-organisation, tolerance. But these properties only emerge from large scale and fully connected neural maps that result in intensive computation coupled with high synaptic communications. We are interested in deploying these powerful models in the embedded context of an autonomous bio-inspired robot learning its environment in realtime. So we study in this paper in what extent these complex models can be simplified and deployed in hardware accelerators compatible with an embedded integration. Thus we propose a Neural Processing Unit designed as a programmable accelerator implementing recent equations close to self-organizing maps and neural fields. The proposed architecture is validated on FPGA devices and compared to state of the art solutions. The trade-off proposed by this dedicated but programmable neural processing unit allows to achieve significant improvements and makes our architecture adapted to many embedded systems.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132519234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite GBW compensation technique for CT ΔΣ modulators with differentiator based ELD compensation","authors":"Chao Chu, J. Anders, J. Becker, M. Ortmanns","doi":"10.1109/NEWCAS.2015.7182112","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182112","url":null,"abstract":"In this work, the mixed-signal differentiator technique for the compensation of excess loop delay has been extended to counteract the effect of the finite GBW of the amplifiers. A RZ DAC is utilized to realize a fast compensation path from the quantizer output to the input of the last integrator. After proper tuning of the scaling coefficients, the original NTF of the modulator can be restored, which has been verified in a 3rd order, single-bit single-loop CT ΔΣ modulator. By using the modified compensation technique, the GBW requirements on the amplifiers can be relaxed significantly while maintaining the SQNR performance and the modulator stability. Consequently, the power consumption of the amplifiers can be drastically reduced.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new method for kTC noise analysis in periodic passive switched-capacitor networks","authors":"Assim Boukhayma, C. Enz","doi":"10.1109/NEWCAS.2015.7182091","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182091","url":null,"abstract":"This work presents a new method for kTC noise calculation in periodic switched capacitor circuits. Two basic applications are overviewed. Namely the switched capacitor low-pass filter and the N-path band-pass filter. Analytical noise calculation using the new method is performed for both examples. The obtained analytical results are confirmed with SpectreRF Pnoise analysis and ELDO transient noise simulations.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Zarudniev, L. Alacoque, A. Tonda, S. Bolis, A. Pouydebasque, F. Jacquet
{"title":"Autofocus performance realization using automatic control approach","authors":"M. Zarudniev, L. Alacoque, A. Tonda, S. Bolis, A. Pouydebasque, F. Jacquet","doi":"10.1109/NEWCAS.2015.7182058","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182058","url":null,"abstract":"Modern autofocus systems are known for their fast response speed and optimized routines of the image processing. Nevertheless, the bottleneck of the autofocus system development is the transformation of the technical specification into the design rules that strictly take in account the specifications and introduce a guarantee of the best performance. In this paper we propose a new approach in autofocus systems design that uses some linear control theory results that allow to obtain the optimal feedback gain in the sense of quadratic sharpness hypothesis. The method proposed in this work allows to improve the existent autofocus systems that are based on the sharpness autofocus using the optimal feedback gain. It is shown that the method is sufficiently generic and can be integrated into an image signal processing unit of a modern camera.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122344730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}