O. Mokrenko, Maria Isabel Vergara Gallego, W. Lombardi, S. Lesecq, C. Albea-Sánchez
{"title":"WSN power management with battery capacity estimation","authors":"O. Mokrenko, Maria Isabel Vergara Gallego, W. Lombardi, S. Lesecq, C. Albea-Sánchez","doi":"10.1109/NEWCAS.2015.7182060","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182060","url":null,"abstract":"Wireless sensor nodes are now cheap and reliable enough to be deployed in different environments. However, their limited energy capacity limits their lifespan. In this paper, a Management strategy at network-level of a set of nodes is implemented, taking into account an estimation of the remaining energy in each sensor node. The control formulation is based on Model Predictive Control with constraints and binary optimization variables, leading to a Mixed Integer Quadratic Programming problem. The estimation of the remaining energy in batteries must be simple enough to be implemented in low-cost, low-power, low-computational-capability sensor nodes.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dual-phase 18V 280μA charge pump with active switches and passive level shifter for low-voltage high-density capacitors","authors":"V. Michal, D. Cottin, Nicolas Marty, P. Arno","doi":"10.1109/NEWCAS.2015.7182026","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182026","url":null,"abstract":"This paper describes the implementation of a high-output current charge pump with passive level shifters, aiming the reliable driving of internal active switches. The technique described here enables advantageous use of high-density integrated Metal-Insulator-Metal (MIM) capacitors with low breakdown voltage, and active switches (MOS transistors). This enables to obtain high power density integration. In addition, capacitor area optimization and feedback control allowing generate constant output voltage are discussed. The 10MHz charge pump was integrated in 0.13μm CMOS process. Thanks to extra epitaxial trench isolation, 18V output voltage with the output current ranging up to 280μA is reached. The target application is the quadrature/frequency compensation of a 3-axis vibratory MEMS Gyroscope.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129558997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chuan Shan, E. Zianbetov, F. Anceau, O. Billoint, D. Galayko
{"title":"A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs","authors":"Chuan Shan, E. Zianbetov, F. Anceau, O. Billoint, D. Galayko","doi":"10.1109/NEWCAS.2015.7182059","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182059","url":null,"abstract":"This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in large digital systems on chip. The originality of the work is in the use of a solution essentially based on digital circuits. This offers many opportunities for implementation of different algorithms of synchronization, depending on the application context and operational conditions. The synchronization algorithm is based on a PI control applied to the phase error measured between neighbors. In this way, the global synchronization is achieved through a local control: such an architecture is compatible with the concept of networks on chip, a largely spread concept in the worlds of VLSI circuits. The paper presents two prototypes demonstrating the feasibility and reliability of the proposed solution for synchronization.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128021813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Frégonèse, R. D’Esposito, M. D. Matos, Andreas Kohler, C. Maneux, T. Zimmer
{"title":"Substrate-coupling effect in BiCMOS technology for millimeter wave applications","authors":"S. Frégonèse, R. D’Esposito, M. D. Matos, Andreas Kohler, C. Maneux, T. Zimmer","doi":"10.1109/NEWCAS.2015.7181981","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7181981","url":null,"abstract":"This paper presents a detailed analysis of substrate coupling effects. Two types of coupling are considered. (i) Coupling from the device to the substrate and (ii) coupling between two neighboring devices. To assess the substrate coupling effect, specific test-structures have been designed for the mmW characterization. Various devices dimensions and distance between two neighboring devices have been fabricated for investigation. In addition, the associated deembedding structures have also been added on the test-structure such as the open, short, open and open-pad structures. Finally, S parameters measurements are performed up to 110 GHz and the substrate-coupling is investigated. To validate the analysis, Sentaurus TCAD simulations are used. A comparison between the S-parameters measurements and TCAD results is given. Finally, a scalable compact model based on lumped elements is proposed for the circuit design in the sub-THz range.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127204986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Khaled A. Helal, Sameh Attia, Tawfik Ismail, H. Mostafa
{"title":"Priority-select arbiter: An efficient round-robin arbiter","authors":"Khaled A. Helal, Sameh Attia, Tawfik Ismail, H. Mostafa","doi":"10.1109/NEWCAS.2015.7182062","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182062","url":null,"abstract":"Round robin arbiter (RRA) is a critical block in nowadays designs. It is widely found in System-on-chips and Network-on-chips. The need of an efficient RRA has increased extensively as it is a limiting performance block. In this paper, we deliver a comparative review between different RRA architectures found in literature. We also propose a novel efficient RRA architecture. The FPGA implementation results of the previous RRA architectures and our proposed one are given, that show the improvements of the proposed RRA.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Saffari, M. Taherzadeh‐Sani, A. Basaligheh, F. Nabki, M. Sawan
{"title":"Low-energy CMOS common-drain power amplifier for short-range applications","authors":"P. Saffari, M. Taherzadeh‐Sani, A. Basaligheh, F. Nabki, M. Sawan","doi":"10.1109/NEWCAS.2015.7182047","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182047","url":null,"abstract":"In this paper, a power amplifier implemented with a common-drain structure is introduced. With proper input matching, this structure is shown to provide a reasonable power gain and superior linearity and efficiency in comparison to other low-power topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the low-voltage variations across the gate-source capacitance. This power amplifier is suitable for low-power and short-range applications such as Bluetooth Low Energy (BLE). Based on the calculated S-parameters, the operation frequency of this amplifier and its design trade-offs are presented, along with a comparison with competitive topologies. The design is simulated in a 0.13 μm CMOS technology, operates with a 1.2 V supply, and provides a power gain of 8.5 dB with a DC power consumption of 3.6 mW. The input 1-dB compression point is 2.2 dBm, yielding a power added efficiency of 43%.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"435 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel ultrasound imaging technique for portable and high speed imaging","authors":"Swetha S. George, Roland Cheng, Z. Ignjatovic","doi":"10.1109/NEWCAS.2015.7182114","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182114","url":null,"abstract":"In this work, a novel technique for ultrasound imaging named Computational Ultrasound has been developed. The computational ultrasound imaging operation involves sending and receiving unfocused echo pulses which are spatio-temporally apodized with random binary sequences. The single channel of acquired RF data is then decoded using convex optimization to obtain the image. The proposed system reduces or eliminates side lobes and speckle noise while providing good image quality only for a fraction of the cost and area of a conventional ultrasound system. Simulations show that computational ultrasound can successfully image sub-wavelength features at the expense of image quality.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, H. Fatemi, J. P. D. Gyvez, Rajesh K. Gupta
{"title":"Supervised learning based model for predicting variability-induced timing errors","authors":"Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, H. Fatemi, J. P. D. Gyvez, Rajesh K. Gupta","doi":"10.1109/NEWCAS.2015.7182029","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182029","url":null,"abstract":"Circuit designers typically combat variations in hardware and workload by increasing conservative guardbanding that leads to operational inefficiency. Reducing this excessive guardband is highly desirable, but causes timing errors in synchronous circuits. We propose a methodology for supervised learning based models to predict timing errors at bit-level. We show that a logistic regression based model can effectively predict timing errors, for a given amount of guardband reduction. The proposed methodology enables a model-based rule method to reduce guardband subject to a required bit-level reliability specification. For predicting timing errors at bit-level, the proposed model generation automatically uses a binary classifier per output bit that captures the circuit path sensitization. We train and test our model on gate-level simulations with timing error information extracted from an ASIC flow that considers physical details of placed-and-routed single-precision pipelined floating-point units (FPUs) in 45nm TSMC technology. We further assess the robustness of our modeling methodology by considering various operating voltage and temperature corners. Our model predicts timing errors with an average accuracy of 95% for unseen input workload. This accuracy can be used to achieve a 0%-15% guardband reduction for FPUs, while satisfying the reliability specification for four error-tolerant applications.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133573550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New TSV-Based applications: Resonant inductive coupling, variable inductor, power amplifier, bandpass filter, and antenna","authors":"K. Salah, Y. Ismail","doi":"10.1109/NEWCAS.2015.7182000","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182000","url":null,"abstract":"This paper presents new TSV-Based applications such as resonant inductive coupling, variable Inductor, power amplifier, bandpass filter, and antenna. These proposed systems use a spiral inductor built using TSV technology. The Resonant Inductive Coupling system increases the amount of magnetic flux linked between coils and improves the power transmission significantly. A proposed architecture based on TSV technology for a variable bridge spiral inductor is demonstrated and characterized. Where, we can obtain different values for the inductor according to the switch state, whether it is ON or OFF. In addition, TSV is used to construct transformer-coupled power amplifier. A new architecture for on-chip bandpass filters, based on through silicon via (TSV) technology. This architecture is the first in literature. According to the simulation results, the TSV-based bandpass filter has an insertion loss of 1.5 dB at 90 GHz and 20 GHz passband from 80 to 100 GHz. This band can be tuned by changing the dimensions of the coupled TSVs. TSV are also used to build an antenna on high resistivity substrate. The characteristic of this antenna is a function of TSV diameter, TSV length, and silicon resistivity. Compared to conventional on-chip antennas who suffers from low gain and low radiation efficiency, our novel antenna provides better performance parameters such as higher radiation pattern efficiency and higher gain as the antenna delivers a high gain of 5.8 dBi and the radiation efficiency is 86% over the prescribed range of frequencies. The proposed antenna is centered at 90 GHz with 20 GHz bandwidth. The overall area of the proposed antenna is 400μm×100μm. Building the antenna using TSV technology not only improves the performance, but also improves the isolation between the antenna and other active circuits.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122976841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Bao, Bart Stukken, J. Stals, Caikou Chen, L. Claesen
{"title":"Quantitative comparison of lossless video compression for multi-camera stereo and view interpolation applications","authors":"Yu Bao, Bart Stukken, J. Stals, Caikou Chen, L. Claesen","doi":"10.1109/NEWCAS.2015.7182116","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182116","url":null,"abstract":"Computational video multi-camera systems allow novel applications such as stereo-vision and view interpolation. The computational- as well as communication and storage requirements for real-time multi-camera video are huge. High quality stereo- and view interpolation applications require the accurate combination of detailed image features in two or more cameras. The use of lossy video compression algorithms often lowers the accuracy of small details and textures that are probably not noticeable by a human viewer, but that are crucial in disparity calculations, matching, video stitching and 3D model synthesis. This paper makes a quantitative comparison of two lossless video compression methods. The intention is to use them for efficient implementation in System-on-Chip (SoC) architectures in computational camera systems. The methods compared are based on predictive-corrective compression and Huffman encoding as well as derived methods. For efficient hardware implementation alternative methods for the use of the Huffman coding are investigated. The comparison includes the use of Huffman encoding parameters from previous frames in the compression of current frames.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123014794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}