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2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)最新文献

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A new digital locking MPPT control for ultra low power energy harvesting systems 一种用于超低功耗能量收集系统的新型数字锁定MPPT控制
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182101
Ayman Eltaliawy, H. Mostafa, Y. Ismail
{"title":"A new digital locking MPPT control for ultra low power energy harvesting systems","authors":"Ayman Eltaliawy, H. Mostafa, Y. Ismail","doi":"10.1109/NEWCAS.2015.7182101","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182101","url":null,"abstract":"This paper presents a new control technique for maximum power delivery of solar energy harvesting systems. The new technique is based on studying the solar cell characteristics, then determining the trajectory of the maximum power across different lighting conditions. The study is based on connecting the solar cell to the power converter, and finding a relationship between the charge pump optimum frequency and the solar cell optimum voltage that delivers the maximum power of the solar cell. The goal of the control unit is to match this frequency-voltage relationship without sensing circuits and/or decision generation circuits. The solar model used maximally delivers 1.5mW, the open circuit voltage is below 550mV. The harvester should deliver a 1.2 V supply voltage. The control unit consists of an 8-bit low power SAR analog-to-digital converter, exponential decoder and a digitally-controlled oscillator. The control unit power consumption is less than 120μW. The power efficiency reaches 43.6% at 975μW available solar power. The technology used for simulations is Global Foundaries 65 nm CMOS.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115491615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-efficient digital design through inexact and approximate arithmetic circuits 通过非精确和近似算术电路进行节能数字设计
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182028
Vincent Camus, Jeremy Schlachter, C. Enz
{"title":"Energy-efficient digital design through inexact and approximate arithmetic circuits","authors":"Vincent Camus, Jeremy Schlachter, C. Enz","doi":"10.1109/NEWCAS.2015.7182028","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182028","url":null,"abstract":"Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error tolerant applications involving perceptive or statistical outputs. This paper reviews two established techniques applicable to arithmetic units: circuit pruning and carry speculation. A critical comparative study is carried out considering several error metrics.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach 利用高效的事件驱动方法对任意有序VSCP-PLL进行建模和PVT表征
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182081
E. Ali, W. Rahajandraibe, N. Tall, F. Haddad, C. Hangmann, C. Hedayat
{"title":"Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach","authors":"E. Ali, W. Rahajandraibe, N. Tall, F. Haddad, C. Hangmann, C. Hedayat","doi":"10.1109/NEWCAS.2015.7182081","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182081","url":null,"abstract":"The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for 2nd and 3rd order PLL is achieved respectively.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114683367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Singular value decomposition FPGA implementation for tactile data processing 触觉数据处理的奇异值分解FPGA实现
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182094
A. Ibrahim, M. Valle, L. Noli, H. Chible
{"title":"Singular value decomposition FPGA implementation for tactile data processing","authors":"A. Ibrahim, M. Valle, L. Noli, H. Chible","doi":"10.1109/NEWCAS.2015.7182094","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182094","url":null,"abstract":"Embedded electronic systems for tactile data processing capture the attention of recent researchers because of its importance in many domains. Machine learning based on tensorial kernel approach has proven its effectiveness in processing tactile information. Computing tensorial kernel corresponds to computing the singular value decomposition. This paper presents an FPGA implementation of singular value decomposition for tensorial kernel computation. The design is implemented for an arbitrary m×n matrix with fixed point arithmetic. The results figure out a tradeoff between the accuracy of computation and the input data resolution. The experimental results demonstrate the efficiency of our design by increasing the accuracy of computation and by providing comparable results in terms of time latency.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117116292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A digital blind background calibration algorithm for pipelined ADC 一种用于流水线ADC的数字盲背景校正算法
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182043
Shengjing Li, Weitao Li, Fule Li, Zhihua Wang, Chun Zhang
{"title":"A digital blind background calibration algorithm for pipelined ADC","authors":"Shengjing Li, Weitao Li, Fule Li, Zhihua Wang, Chun Zhang","doi":"10.1109/NEWCAS.2015.7182043","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182043","url":null,"abstract":"This work presents a blind background calibration algorithm for correcting inter-stage gain error and capacitor mismatches in pipelined ADC. Based on the analysis of the density of specific output codes, the algorithm stores the information of the codes and needs only 80 registers. And there is no need to modify the analog circuits, which simplifies the design. Besides, since there is no multiplication or division in the digital logic, the algorithm can be implemented with a low hardware overhead, which lowers the power dissipation. For verification, a 14-bit 150MS/s ADC is fabricated in 130nm CMOS process. At 15.5MHz input signal, SDNR/SFDR improved from 66.8dB/78.57dBc to 69.7dB/87.3dBc and INL dropped from 8LSB to 3LSB after calibration.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116240550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An automated ear identification system using Gabor filter responses 使用Gabor滤波器响应的自动耳识别系统
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182085
A. Meraoumia, S. Chitroub, A. Bouridane
{"title":"An automated ear identification system using Gabor filter responses","authors":"A. Meraoumia, S. Chitroub, A. Bouridane","doi":"10.1109/NEWCAS.2015.7182085","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182085","url":null,"abstract":"About some years ago, several biometric technologies are considered mature enough to be a new tool for security and ear-based person identification is one of these technologies. This technology provides a reliable, low cost and user-friendly viable solution for a range of access control applications. In this paper, we propose an efficient online personal identification system based on ear images. In this purpose, the identification algorithm aims to extract, for each ear, a specific set of features. Based on Gabor filter response, three ear features have been used in order to extract different and complementary information: phase, module and a combination of the real and imaginary parts. Using these features, several combinations are tested in the fusion phase in order to achieve an optimal multi-representation system which leads to a better identification accuracy. The obtained experimental results show that the system yields the best performance for identifying a person and it is able to provide the highest degree of biometrics-based system security.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115391197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Time-domain simulation of quantization noise mixing and charge pump device noise in fractional-N PLLs 分数n锁相环中量化噪声混合和电荷泵器件噪声的时域仿真
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182079
M. Kucharski, F. Herzel, D. Kissinger
{"title":"Time-domain simulation of quantization noise mixing and charge pump device noise in fractional-N PLLs","authors":"M. Kucharski, F. Herzel, D. Kissinger","doi":"10.1109/NEWCAS.2015.7182079","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182079","url":null,"abstract":"In this paper we model phase noise and spurious tones (spurs) for a fractional-N phase-locked loop (PLL) with static phase offset. The phase detector (PD) input-output characteristic around the bias point is approximated by a parabolic function. Using a MATLAB code, phase noise spectrum and fractional spurs are calculated as a function of slope and curvature of the PD characteristic. The dependence of the PLL output spectrum on PD nonlinearity and rms phase error at the PD input is discussed and compared with theoretical results. A close agreement with theoretical predictions is observed.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123335544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Auto tuning system for a half bridge resonant converter using a synchronous switched capacitor 采用同步开关电容的半桥谐振变换器自动调谐系统
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182052
Xusheng Wang, Ming Zhang, X. Ren, F. Rodes, R. Denieport
{"title":"Auto tuning system for a half bridge resonant converter using a synchronous switched capacitor","authors":"Xusheng Wang, Ming Zhang, X. Ren, F. Rodes, R. Denieport","doi":"10.1109/NEWCAS.2015.7182052","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182052","url":null,"abstract":"In this paper, an auto tuning system that uses a variable synchronous switched capacitor for controlling the resonant frequency of the tank circuit of a half bridge voltage mode resonant converter for High intensity focused ultrasound (HIFU) applications is presented. The presented auto tuning system using a switched capacitor instead of a large inductor in the classical tuning topology. Hence, there will be no need of bulky magnetic components. which makes it naturally comply with the Magnetic Resonance Imaging (MRI) compatibility regulations. The designed circuit works under 1MHz, which is simulated in a CMOS 0.35μm technology. The required performances have been confirmed by simulation results.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123294707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1V 830μW full-band ZigBee receiver front-end with current-reuse and Gm-boosting techniques 一个1V 830μW全频带ZigBee接收器前端，具有电流复用和gm增强技术
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182015
Zengqi Wang, Zhiqun Li
{"title":"A 1V 830μW full-band ZigBee receiver front-end with current-reuse and Gm-boosting techniques","authors":"Zengqi Wang, Zhiqun Li","doi":"10.1109/NEWCAS.2015.7182015","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182015","url":null,"abstract":"A low-voltage low-power CMOS ZigBee receiver front-end supporting 780/868/915/2400MHz bands is presented in this paper. The wideband common-gate (CG) low noise amplifier (LNA) and the I/Q current-commutating mixer are merged in a single circuit, sharing the bias current. Active trans-conductance (gm) boosting technique is utilized in the design of the presented receiver front-end. The topology and optimization method of the presented front-end are shown. Post-layout simulation results for 180nm RF CMOS implementations show the conversion gain is 26.5dB at 780/868/915MHz bands and 19.5dB at 2400MHz band. The minimum simulated NF is 6.5dB. The receiver front-end consumes 830μW from a 1V DC supply and the active size of core circuit is 0.0276mm2.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122182930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Colored clock jitter model in audio continuous-time ΣΔ modulators 音频连续时间ΣΔ调制器中的彩色时钟抖动模型
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) Pub Date : 2015-06-07 DOI: 10.1109/NEWCAS.2015.7182021
C. D. Berti, P. Malcovati, L. Crespi, A. Baschirotto
{"title":"Colored clock jitter model in audio continuous-time ΣΔ modulators","authors":"C. D. Berti, P. Malcovati, L. Crespi, A. Baschirotto","doi":"10.1109/NEWCAS.2015.7182021","DOIUrl":"https://doi.org/10.1109/NEWCAS.2015.7182021","url":null,"abstract":"In this paper the effect of colored clock jitter on audio continuous-time ΣΔ modulators is studied. The results demonstrate the importance of using the correct model for the jitter on the clock signal, especially when it is generated by a phase-locked loop, as it is the case in most audio applications. The paper demonstrates that the popular clock signal model with white jitter noise spectrum leads to worse ΣΔ modulator performance than a more realistic model with colored jitter noise spectrum. Indeed, such a model allows the designer to obtain more reliable simulation results, in order to choose the most suitable architecture and size correctly the circuit components to achieve the desired design target, leading to power consumption and area optimization.","PeriodicalId":404655,"journal":{"name":"2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)","volume":"663 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125581516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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