A digital blind background calibration algorithm for pipelined ADC

Abstract

This work presents a blind background calibration algorithm for correcting inter-stage gain error and capacitor mismatches in pipelined ADC. Based on the analysis of the density of specific output codes, the algorithm stores the information of the codes and needs only 80 registers. And there is no need to modify the analog circuits, which simplifies the design. Besides, since there is no multiplication or division in the digital logic, the algorithm can be implemented with a low hardware overhead, which lowers the power dissipation. For verification, a 14-bit 150MS/s ADC is fabricated in 130nm CMOS process. At 15.5MHz input signal, SDNR/SFDR improved from 66.8dB/78.57dBc to 69.7dB/87.3dBc and INL dropped from 8LSB to 3LSB after calibration.