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The AES in a systolic fashion: Implementation and results of Celator processor 系统方式的 AES：Celator 处理器的实现和结果
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674870
Daniele Fronte, A. Pérez, Eric Payrat
{"title":"The AES in a systolic fashion: Implementation and results of Celator processor","authors":"Daniele Fronte, A. Pérez, Eric Payrat","doi":"10.1109/ICECS.2008.4674870","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674870","url":null,"abstract":"A multi-algorithm Crypto-Co-Processor called Celator is presented. Celator architecture is based on a 4times4 Processing Elements systolic array, a Sequencer with a Finite State Machine (FSM) and a local memory, the Celator RAM (CRAM). Data are encrypted or decrypted by the PE array. The whole system architecture around Celator includes a Central Processing Unit (CPU) and an Interface unit between the CPU and Celator. The Sequencer controls the PE array and manages all the data transfers between the PE array and the CPU. Three multiplexers per PE allow the reconfigurability of the data path. The FSM instructions are stored in the CRAM and can be changed by the CPU: therefore the FSM is also reconfigurable. This paper focuses on the implementation of the Advanced Encryption Standard (AES) transformations on Celator. Celator can perform an AES encryption in 580 clock cycles in Electronic Codebook mode, which is less than with a general purpose processor. Finally we report performance comparisons among Celator, ARM 7 TDMI, ARM 9 and AVR microprocessors, as well as with some AES dedicated and dynamically reconfigurable circuits.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128561316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Resistorless tuneable KHN-filter in current mode with CCCIIs and grounded capacitors 具有cccii和接地电容的电流模式无电阻可调谐khn滤波器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674856
S. Yamaçli, Sadri Özcan, H. Kuntman
{"title":"Resistorless tuneable KHN-filter in current mode with CCCIIs and grounded capacitors","authors":"S. Yamaçli, Sadri Özcan, H. Kuntman","doi":"10.1109/ICECS.2008.4674856","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674856","url":null,"abstract":"In this work, an electronically tuneable resistorless Kerwin-Huelsman-Newcomb (KHN) filter circuit is proposed, employing multi-output CCCIIs (MO-CCCIIs) and grounded capacitors. The new circuit provides highpass, bandpass and lowpass responses simultaneously without any matching condition. Pole frequency and quality factor of the new circuit can be tuned electronically and orthogonally via biasing currents of MO-CCCIIs. SPICE simulation results verifying the theory are also included.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Magnetic microsystem with extended dynamic range and absolute accuracy 具有扩展动态范围和绝对精度的磁微系统
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674995
A. Sešek, J. Trontelj
{"title":"Magnetic microsystem with extended dynamic range and absolute accuracy","authors":"A. Sešek, J. Trontelj","doi":"10.1109/ICECS.2008.4674995","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674995","url":null,"abstract":"A new concept of magnetic microsystem design is proposed to increase the dynamic range and absolute accuracy. The measured result on the realized microsystem of the noise density is better than 80 nT/radic(Hz) in frequency range from DC to 10 kHz. The absolute accuracy is obtained by integrated continuous autocalibration.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Weighted criteria for RF power amplifiers identification in wide-band context 宽带环境下射频功率放大器识别的加权准则
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674819
Sonia Saied Bouajina, Mériem Jaïdane, F. Ghannouchi
{"title":"Weighted criteria for RF power amplifiers identification in wide-band context","authors":"Sonia Saied Bouajina, Mériem Jaïdane, F. Ghannouchi","doi":"10.1109/ICECS.2008.4674819","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674819","url":null,"abstract":"Modeling accurately RF power amplifiers (PAs) is an essential first step for predistortion and identification purposes. In WCDMA context, we prove that inaccurate results of identification are achieved because of the inadequacy of the classical criteria of least squares fitting to the WCDMA input pdf. The performances of the identification can be enhanced through a weighted criteria taking into account AM/AM dispersion for low input amplitudes. In this paper, the weighted criteria is validated for 1- carrier WCDMA input and two RF PAs, considering polynomial memoryless model and multibranch polynomial model.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130225245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
AER filtering using GLIDER: VHDL cellular automata description AER滤波使用GLIDER: VHDL元胞自动机描述
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674928
A. Linares-Barranco, J. Sevillano, M. Obaidat, N. Ferrando, J. Cerdá, Daniel Cascado Caballero, G. Jiménez-Moreno, A. C. Balcells
{"title":"AER filtering using GLIDER: VHDL cellular automata description","authors":"A. Linares-Barranco, J. Sevillano, M. Obaidat, N. Ferrando, J. Cerdá, Daniel Cascado Caballero, G. Jiménez-Moreno, A. C. Balcells","doi":"10.1109/ICECS.2008.4674928","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674928","url":null,"abstract":"Cellular automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the address-event-representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop complex, multilayer, multichip neuromorphic systems. This paper presents the fusion of both bio-inspired solutions for implementing a vision filter based on 3times3 convolutions. The GLIDER software tool for developing CA has been used to implement the filter in VHDL and synthesize it into the Spartan II 200 of the USB-AER.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128708134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Overview of maximum power point tracking control techniques used in photovoltaic systems 光伏系统中最大功率点跟踪控制技术综述
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675049
C. Jaen, Cristian Moyano, Xavier Santacruz, J. Pou, A. Arias
{"title":"Overview of maximum power point tracking control techniques used in photovoltaic systems","authors":"C. Jaen, Cristian Moyano, Xavier Santacruz, J. Pou, A. Arias","doi":"10.1109/ICECS.2008.4675049","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675049","url":null,"abstract":"Nowadays power supply systems based on photovoltaic cells have two main drawbacks even the primary energy is free and renewable. They are production cost and efficiency. In order to increase their efficiency should be interesting that the energy transfer between cells and load was done at maximum level. In this paper an overview of control techniques oriented to obtain the maximum power point tracking (MPPT) is presented. Then a specific method is fully developed and finally, some simulation and experimental results are also included.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A pseudo-differential transmitting circuit causing reduced common-mode current variations 一种减小共模电流变化的伪差分传输电路
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674780
F. Broydé, E. Clavelier
{"title":"A pseudo-differential transmitting circuit causing reduced common-mode current variations","authors":"F. Broydé, E. Clavelier","doi":"10.1109/ICECS.2008.4674780","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674780","url":null,"abstract":"This paper introduces a new type of pseudo-differential transmitting circuit (TX circuit) such that signaling ideally produces no common-mode current variations in the terminals intended to be connected to the interconnection. These terminals are expected to behave as if the TX circuit was composed of a floating circuit and a two-terminal circuit element connected between the common terminal and ground. This is in contrast with conventional pseudo-differential TX circuits in which the generation of signals produces a variable return current flowing in the reference conductor. We present a detailed design and provide simulation results. We then consider the implementation of this TX circuit in a pseudo-differential link. This link is capable of low reflections and a reduced common-mode current. It consequently offers a good protection against external crosstalk.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127234098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL 基于SystemC-VHDL的主动可重构板的软硬件系统协同验证
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675064
Y. Basile-Bellavance, E. Lepercq, Y. Blaquière, Y. Savaria
{"title":"Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL","authors":"Y. Basile-Bellavance, E. Lepercq, Y. Blaquière, Y. Savaria","doi":"10.1109/ICECS.2008.4675064","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675064","url":null,"abstract":"This paper reports on the challenges encountered, and the solutions adopted in the hardware and software co-verification of a wafer-scale integrated (WSI) system. The WaferBoardtrade is designed for rapid prototyping of complex digital systems. This advanced technology embeds a smart active substrate that can be configured through a set of JTAG ports to interconnect digital integrated chips placed on its surface. The software that generates JTAG bit streams and the related hardware infrastructure embedded in the WaferBoardtrade must be validated early and efficiently in the design process to improve productivity. The system co-verification methodology presented in this paper relies on a unified SystemC-VHDL environment making the design and verification tasks more effective. Results demonstrate that the simulation time complexity grows quadratically with the circuit size in number of gates if one JTAG port is used.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126339838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a rad-hard library of digital cells for space applications 空间应用数字单元的抗辐射库设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674813
A. Stabile, V. Liberali, C. Calligaro
{"title":"Design of a rad-hard library of digital cells for space applications","authors":"A. Stabile, V. Liberali, C. Calligaro","doi":"10.1109/ICECS.2008.4674813","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674813","url":null,"abstract":"This paper proposes a design methodology for a digital library of cells resistant to cosmic radiation. Most important effects due to radiation are avoided or mitigated using ad hoc design techniques. Fault injection techniques are used to validate the design. Simulations results demonstrate that the cells designed in a 180 nm CMOS technology are tolerant to 1.5 mA current peak due to interaction with a single high-energy particle.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121501707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
High speed and ultra low voltage CMOS latch 高速超低电压CMOS锁存器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674814
Y. Berg, O. Mirmotahari, S. Aunet
{"title":"High speed and ultra low voltage CMOS latch","authors":"Y. Berg, O. Mirmotahari, S. Aunet","doi":"10.1109/ICECS.2008.4674814","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674814","url":null,"abstract":"In this paper we present a novel ultra-low-voltage (ULV) CMOS latch and a flip-flop. The gates offer increased speed compared to other CMOS logic styles for ultra low supply voltages. The timing detail is discussed and an ULV latch is presented. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary CMOS gate assuming a very low supply voltage. The latch may be applied in a ULV flip-flop as well. The simulated data for the latch presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133603071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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