High speed and ultra low voltage CMOS latch

Abstract

In this paper we present a novel ultra-low-voltage (ULV) CMOS latch and a flip-flop. The gates offer increased speed compared to other CMOS logic styles for ultra low supply voltages. The timing detail is discussed and an ULV latch is presented. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary CMOS gate assuming a very low supply voltage. The latch may be applied in a ULV flip-flop as well. The simulated data for the latch presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.