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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)最新文献

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Resistor layout techniques for enhancing yield in ratio-critical monolithic applications 在比例关键的单片应用中提高良率的电阻布局技术
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986163
Y. Lin, Randall L. Geiger
{"title":"Resistor layout techniques for enhancing yield in ratio-critical monolithic applications","authors":"Y. Lin, Randall L. Geiger","doi":"10.1109/MWSCAS.2001.986163","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986163","url":null,"abstract":"A new strategy for the layout of integrated resistors that minimizes yield loss due to random sheet resistance variations for a given area in ratio-critical applications is introduced. The strategy is based upon the optimal partitioning of area between the resistors that must be ratio-matched and on the practical realization of the partitioned resistors with unit resistor cells. This strategy provides substantial improvements in yield over what is achievable with most existing layout strategies when large and accurate resistor ratios are required.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126647673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An RF CMOS cascode LNA with current reuse and inductive source degeneration 具有电流复用和感应源退化的RF CMOS级联LNA
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986314
H. Fouad, K. Sharaf, E. El-Diwany, H. El-Hennawy
{"title":"An RF CMOS cascode LNA with current reuse and inductive source degeneration","authors":"H. Fouad, K. Sharaf, E. El-Diwany, H. El-Hennawy","doi":"10.1109/MWSCAS.2001.986314","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986314","url":null,"abstract":"An RF CMOS Low-Noise Amplifier (LNA) is proposed using a current reuse technique (CRT) to increase the amplifier transconductance without increasing power dissipation. The circuit was simulated and designed with 0.5 /spl mu/m CMOS MOSIS process. At 1 GHz, the LNA noise figure (NF) is 2.7 dB, forward gain is 21.6 dB and reverse isolation is -42.5 dB. The LNA consumes 20.3 mW from a 2.2 V power supply.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126890400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A deep sub-micron SRAM cell design and analysis methodology 一种深亚微米SRAM单元设计与分析方法
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986322
D. Kang, Yong-Bin Kim
{"title":"A deep sub-micron SRAM cell design and analysis methodology","authors":"D. Kang, Yong-Bin Kim","doi":"10.1109/MWSCAS.2001.986322","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986322","url":null,"abstract":"This paper presents a comprehensive SRAM design and diagnosis methodology including optimization paradigms on cell stability test against power supply fluctuations, SRAM access time, bit line voltage switching, and static noise margin analysis of a SRAM cell.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"91 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
D-MRC: digitally programmable MOS resistive circuit D-MRC:数字可编程MOS电阻电路
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986152
E. Alarcón, H. Martínez, E. Vidal, J. Madrenas, A. Poveda
{"title":"D-MRC: digitally programmable MOS resistive circuit","authors":"E. Alarcón, H. Martínez, E. Vidal, J. Madrenas, A. Poveda","doi":"10.1109/MWSCAS.2001.986152","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986152","url":null,"abstract":"This paper presents the D-MRC circuit, a mixed-signal cell which operates as a digitally-controlled differential resistor, and that is suited to programmable continuous-time MOSFET-C filter applications. The cell is based on a digitally-controlled extension of the MRC (MOS Resistive Circuit) cell, in which digital tunability is obtained by embedding in the same MRC transistors both the triode-region and switch functions, providing a compact implementation that preserves circuit performance. This cell is of interest for static and dynamic reconfigurability of mixed-signal circuits, as required in multistandard wireless CMOS receivers. The proposed cell has been designed down to the layout level for a particular prototype with 3-bit digital controllability in 0.8 /spl mu/m CMOS technology. Post-layout simulation results validate the functionality of the proposed cell and its application to a digitally-tunable continuous-time MOSFET-C filter.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Two-channel IIR/FIR filter banks with very low-complexity analysis or synthesis filters: finite wordlength effects 具有非常低复杂度分析或合成滤波器的双通道IIR/FIR滤波器组:有限字长效应
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986131
P. Lowenborg, E. Elias, H. Johansson, L. Wanhammar
{"title":"Two-channel IIR/FIR filter banks with very low-complexity analysis or synthesis filters: finite wordlength effects","authors":"P. Lowenborg, E. Elias, H. Johansson, L. Wanhammar","doi":"10.1109/MWSCAS.2001.986131","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986131","url":null,"abstract":"A new class of two-channel IIR/FIR filter banks was introduced by the authors in 2000 with half-band IIR analysis filters and FIR synthesis filters. This type of filter bank features very low-complexity analysis filters and simultaneously a low overall complexity. In this paper, we consider finite-wordlength effects of these filter banks.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121482781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Direct Haar-space control for DC motors 直接haar空间控制直流电机
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986353
A. Gandelli, S. Leva
{"title":"Direct Haar-space control for DC motors","authors":"A. Gandelli, S. Leva","doi":"10.1109/MWSCAS.2001.986353","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986353","url":null,"abstract":"After considering the analysis of a three-phase inverter driving induction motors for railway applications, the authors take into consideration the system formed by a DC motor fed by a chopper. The mathematical analysis has been conducted through Haar functions, a tool based on the general framework of wavelets. The spec advantage consists in being able to solve differential equations by approaching the problem in the Haar domain, instead of adopting a time domain solution. A limited number of Haar coefficients are necessary to perform this task. Especially transient conditions during the starting process can usefully be examined in such a way, putting into evidence specific characteristics of the chopper motor system. An example describing the application of such technique is presented and critically described.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131214564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Induced error-correcting code for 2 bit-per-cell multi-level DRAM 每单元2位多级DRAM的诱导纠错码
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986185
Boris Polianskikh, Z. Zilic
{"title":"Induced error-correcting code for 2 bit-per-cell multi-level DRAM","authors":"Boris Polianskikh, Z. Zilic","doi":"10.1109/MWSCAS.2001.986185","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986185","url":null,"abstract":"Traditionally, memories employ SEC-DED (Single Error Correcting and Double Error Detecting) Error Correcting Codes (ECC). While such codes have been considered for MLDRAM (Multi-Level Dynamic Random Access Memory), their use is inefficient, due to likely double-bit errors in a single cell. For this reason we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows significant increase in reliability of the MLDRAM.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Development strategies for durable hardware language descriptions of analog and mixed signal circuits 模拟和混合信号电路持久硬件语言描述的开发策略
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986280
E. Murphy, S. Bibyk
{"title":"Development strategies for durable hardware language descriptions of analog and mixed signal circuits","authors":"E. Murphy, S. Bibyk","doi":"10.1109/MWSCAS.2001.986280","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986280","url":null,"abstract":"VHDL-AMS, or VHSIC hardware description language - analog and mixed signal extensions is being supported in a variety of design automation tools for circuit design. Although there are a number of published examples on the use of VHDL-AMS for modeling of mixed signal circuits, it is still not clear what are examples of \"best practice\" methods. This paper discusses research efforts to identify analog macros, or descriptions that can be reused by other designers that are possibly targeting different fabrication processes.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132687597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of the ray tracing algorithm used in the XPATCH software 用FPGA实现的光线追踪算法在XPATCH软件中使用
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986208
P. Sundararajan, M. Niamat
{"title":"FPGA implementation of the ray tracing algorithm used in the XPATCH software","authors":"P. Sundararajan, M. Niamat","doi":"10.1109/MWSCAS.2001.986208","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986208","url":null,"abstract":"Ray tracing is one of the most popular and powerful image synthesis technique for creating photo-realistic images. In this research, we focus on the time critical application of ray tracing in the XPATCH software for high-resolution radar simulation and detection. Of particular interest to us is the ray/box intersection algorithm employed in the XPATCH ray tracer for achieving faster execution time. The ray/box algorithm is used to determine whether a ray hits or misses the target enclosed in a rectangular bounded volume.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"21 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132705862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 1.75 GHz inductor-less CMOS low noise amplifier with high-Q active inductor load 具有高q有源电感负载的1.75 GHz无电感CMOS低噪声放大器
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI: 10.1109/MWSCAS.2001.986312
Jhy-Neng Yang, Y. Cheng, Terng-Yin Hsu, Terng-Ren Hsu, Chen-Yi Lee
{"title":"A 1.75 GHz inductor-less CMOS low noise amplifier with high-Q active inductor load","authors":"Jhy-Neng Yang, Y. Cheng, Terng-Yin Hsu, Terng-Ren Hsu, Chen-Yi Lee","doi":"10.1109/MWSCAS.2001.986312","DOIUrl":"https://doi.org/10.1109/MWSCAS.2001.986312","url":null,"abstract":"A 1.75 GHz CMOS inductor-less low noise amplifier with high-Q active inductor load using 0.35 /spl mu/m standard CMOS digital process is presented. In this low noise amplifier, the compact tunable high-Q active inductor load is connected to the common-gate configuration to improve the performance of the high power gain, low power consumption and simple matching characteristics. Not using any passive components results in a reduction of the area of chip and the complexity. HSPICE simulation has been performed to verify the performance of the designed low noise amplifier. It has been shown that the amplifier has a power gain of 24 dB(S21), S11 of -31 dB, S12 of -38.5 dB and S22 of -21.4 dB under 3.3 V power supply with 9.3 mW power consumption around at 1.75 GHz center frequency. The experimental chip fabricated occupies 0.057/spl times/0.056 mm/sup 2/ chip area.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132762264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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