Resistor layout techniques for enhancing yield in ratio-critical monolithic applications

Abstract

A new strategy for the layout of integrated resistors that minimizes yield loss due to random sheet resistance variations for a given area in ratio-critical applications is introduced. The strategy is based upon the optimal partitioning of area between the resistors that must be ratio-matched and on the practical realization of the partitioned resistors with unit resistor cells. This strategy provides substantial improvements in yield over what is achievable with most existing layout strategies when large and accurate resistor ratios are required.