每单元2位多级DRAM的诱导纠错码

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986185

Boris Polianskikh, Z. Zilic

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引用次数: 6

摘要

传统上，存储器采用SEC-DED(单错误校正和双错误检测)纠错码(ECC)。虽然这种代码已经被考虑用于MLDRAM(多层次动态随机存取存储器)，但由于单个单元中可能存在双比特错误，它们的使用效率很低。出于这个原因，我们提出了一种诱导ECC架构，该架构使用ECC的方式是没有常见错误损坏两个比特。感应ECC可以显著提高MLDRAM的可靠性。

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Induced error-correcting code for 2 bit-per-cell multi-level DRAM

Traditionally, memories employ SEC-DED (Single Error Correcting and Double Error Detecting) Error Correcting Codes (ECC). While such codes have been considered for MLDRAM (Multi-Level Dynamic Random Access Memory), their use is inefficient, due to likely double-bit errors in a single cell. For this reason we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows significant increase in reliability of the MLDRAM.

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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