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ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE 一种具有再生无功反馈的112-142GHz功率放大器，在13% PAE下峰值Psat达到17dBm
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902764
A. Visweswaran, Bastien Vignon, Xin-yan Tang, S. Brebels, B. Debaillie, P. Wambacq
{"title":"A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE","authors":"A. Visweswaran, Bastien Vignon, Xin-yan Tang, S. Brebels, B. Debaillie, P. Wambacq","doi":"10.1109/ESSCIRC.2019.8902764","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902764","url":null,"abstract":"A two-way power-combining amplifier operating from 112-142GHz is presented. Integrated in Infineon’s 0.13μm SiGe-BiCMOS technology, it delivers 17dBm of peak saturated power to a 50Ω load at 13% PAE. Five fully-differential, transformer-coupled amplifier stages per path provide 34dB of forward transmission gain. Each 5-stage PA consists of capacitively gain-enhanced pre-drivers operated from 1.5V, followed by an inductively gain-enhanced cascoded driver powered by 3.3V. BJT models relevant at frequencies beyond 100GHz are evaluated to outline the trade-off between stability and gain exploited in this work. The design and layout of a folded, fully-differential, λ/4 power combiner is also presented, along with a full two-port characterization of the power-amplifier prototype.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126185481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO 基于变压器的超低功耗压控振荡器的78秒RMS抖动注入锁定时钟乘法器
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902523
Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane
{"title":"A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","authors":"Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane","doi":"10.1109/ESSCIRC.2019.8902523","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902523","url":null,"abstract":"This paper presents a low jitter performance and low power consumption injection-locked clock multiplier (ILCM) for IoT application in 65-nm CMOS. A transformer-based ultra-low power (ULP) LC-VCO is proposed to minimize the overall power consumption. The introduced capacitor feedback path boosts the VCO loop gain and thus a robust startup can be obtained. The proposed transformer-based VCO achieves −115.1 dBc/Hz at 1 MHz frequency offset with a 97 μW power consumption, which corresponds to a -194 dBc/Hz VCO figure-of-merit (FoM). Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while consuming 210 μW power. A -269 dB FoMJP of jitter and power is achieved by this proposed ILCM, and a -262 dB FoMJRP is obtained while considering the 520 MHz input reference with multiplication factor equals to 5.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114514073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A −81.6dBm Sensitivity Ultrasound Transceiver in 65nm CMOS for Symmetrical Data-Links A−81.6dBm灵敏度超声收发器在65nm CMOS对称数据链路
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902921
Gönenç Berkol, P. Baltus, P. Harpe, E. Cantatore
{"title":"A −81.6dBm Sensitivity Ultrasound Transceiver in 65nm CMOS for Symmetrical Data-Links","authors":"Gönenç Berkol, P. Baltus, P. Harpe, E. Cantatore","doi":"10.1109/ESSCIRC.2019.8902921","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902921","url":null,"abstract":"This paper presents the design and experimental characterization of an ultrasound transceiver. The transceiver includes an on-chip transmitter and a receiver to be used in a symmetric data-link, where each sensor node has limited energy resources and is operated in air or a fluidic environment. The receiver and the transmitter operate from a 0.8V supply and consume 1.18µW and 50µW, respectively, while exchanging data at 1kbps data-rate. The receiver sensitivity is −81.6dBm at a 10°3 Bit Error Rate (BER) level, which enables an experimentally verified transmission over 3.2m in air and a predicted transmission distance in water in the order of 2km, with a measured energy per bit performance of 51.18 nJ/b.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128744285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 57–74-GHz Tail-Switching Injection-Locked Frequency Tripler in 28-nm CMOS 一种基于28纳米CMOS的57 - 74 ghz尾开关注入锁定三倍频器
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902908
Lorenzo Lotti, G. LaCaille, A. Niknejad
{"title":"A 57–74-GHz Tail-Switching Injection-Locked Frequency Tripler in 28-nm CMOS","authors":"Lorenzo Lotti, G. LaCaille, A. Niknejad","doi":"10.1109/ESSCIRC.2019.8902908","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902908","url":null,"abstract":"This letter presents a wideband injection-locked frequency tripler for mm-wave local oscillator generation. Conventional class-C injection is combined with class-D tail-switching, achieving significant extension of the locking range. Theoretical insights on the effectiveness of the proposed technique are provided. A 28-nm CMOS prototype achieves 57–74 GHz operation with 11-mW power consumption, without the need of tuning or calibration.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS 13.5 gb /s 5 mv灵敏度26.8 ps clk - out延迟三锁存器动态比较器
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902790
A. Ramkaj, M. Steyaert, F. Tavernier
{"title":"A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS","authors":"A. Ramkaj, M. Steyaert, F. Tavernier","doi":"10.1109/ESSCIRC.2019.8902790","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902790","url":null,"abstract":"We present a three-stage triple-latch feedforward fully dynamic comparator, with an achievable data rate of 13.5 Gb/s and a BER < 10−12 for input amplitudes as small as 5 mVpp-diff. The combination of a high gain three-stage configuration and an extra parallel feedforward path results in a maximum CLK–OUT delay of only 26.8 ps and a delay slope of 6.4 ps/decade. Furthermore, the cascaded triple-latch architecture with minimized stacking enables a < 70-ps delay across a wide common-mode (VCM) and supply (VDD) range. The prototype comparator in 28-nm bulk CMOS dissipates 2.2 mW at 13.5 Gb/s and 5 mVpp-diff from a 1-V supply, for a core area of 78 µm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121499335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 11 GHz–Bandwidth Variable Gain Ka–Band Power Amplifier for 5G Applications 一种用于5G应用的11 ghz带宽可变增益ka波段功率放大器
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902927
R. Bagger, H. Sjöland
{"title":"An 11 GHz–Bandwidth Variable Gain Ka–Band Power Amplifier for 5G Applications","authors":"R. Bagger, H. Sjöland","doi":"10.1109/ESSCIRC.2019.8902927","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902927","url":null,"abstract":"A Ka–band, 32–43 GHz, differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre–driver, driver and final stage, respectively. To enable use of 2.7 V supply, a cascode topology was employed in all three stages. The input is 80 Ω differential and the output load is 50 Ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB, including output losses of 2–2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front–end design, and its output thus faces an antenna interface with integrated LNA and TX/RX switches, and the input is connected to an on-chip variable gain amplifier.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS 具有接收端PWM(时域)前馈均衡的PAM-8有线收发器，在65nm CMOS中工作范围为12至39.6 gb /s
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902575
Yusang Chun, Ashwin Ramachandran, Tejasvi Anand
{"title":"A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS","authors":"Yusang Chun, Ashwin Ramachandran, Tejasvi Anand","doi":"10.1109/ESSCIRC.2019.8902575","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902575","url":null,"abstract":"A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129129975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 128 × 128 SPAD Dynamic Vision-Triggered Time of Flight Imager 128 × 128 SPAD动态视觉触发飞行时间成像仪
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902693
Francesco Mattioli Della Rocca, Hanning Mai, S. W. Hutchings, T. A. Abbas, A. Tsiamis, Peter Lomax, I. Gyöngy, N. Dutton, R. Henderson
{"title":"A 128 × 128 SPAD Dynamic Vision-Triggered Time of Flight Imager","authors":"Francesco Mattioli Della Rocca, Hanning Mai, S. W. Hutchings, T. A. Abbas, A. Tsiamis, Peter Lomax, I. Gyöngy, N. Dutton, R. Henderson","doi":"10.1109/ESSCIRC.2019.8902693","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902693","url":null,"abstract":"A 128 x 128 SPAD motion detection-triggered time of flight (ToF) sensor is implemented in 40nm CMOS. The sensor combines vision and ToF ranging functions to only acquire depth frames when inter-frame intensity changes are detected. The 40µm x 20µm pixel integrates two 16-bit time-gated counters to acquire ToF histograms and repurposes them to compare two vision frames without requirement for additional out-of-pixel frame memory resources. An embedded ToF and vision processor performs on-chip vision frame comparison and binary frame output compression as well as controlling the time-resolved histogram sampling. The sensor achieves a maximum 20kfps in vision modality and 500fps in motion detection-triggered ToF over a measured 2.55m range with 1.6cm accuracy. The vision function reduces the sensor power consumption by 70% over continuous ToF operation and allows the sensor to gate the ToF laser emitter to reduce the system power when no motion activity is observed.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe 直接转换I-Q发射器前端180ghz与80ghz带宽在130nm SiGe
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902879
Paul Stärke, Xin Xu, C. Carta, F. Ellinger
{"title":"Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe","authors":"Paul Stärke, Xin Xu, C. Carta, F. Ellinger","doi":"10.1109/ESSCIRC.2019.8902879","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902879","url":null,"abstract":"This work presents an integrated mm-wave transmitter front-end with independent in-phase and quadrature paths for carrier frequencies around 180 GHz. The up-conversion units consist of a double-balanced active mixer with baseband (IF) buffer, local oscillator (LO) driver and RF power amplifier (PA). A passive 90° hybrid generates the quadrature LO signal and a power combiner joins the PA outputs. The IF-to-RF conversion gain is 10 dB, with an RF bandwidth of 80 GHz. The design supports binary and higher order modulation schemes and exhibits an IF input referred 1-dB compression point of −11 dBm. The saturated output power is 3.5 dBm per path and an LO level of −5 dBm is sufficient for an optimal operation. The total power consumption is 151 mW per path. The final chip occupies an area of 1.4 mm2 and is fabricated in a 130 nm SiGe BiCMOS process with a maximum oscillation frequency of 450 GHz. The main application of this circuit is ultra-wideband short-range communication with data rates beyond 100 Gbit/s.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123536862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS 用于2-5GHz 28nm CMOS波束导向接收机的延时本相移发生器
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902864
Yury Antonov, M. Valkama, M. Kosunen, J. Ryynänen, M. Zahra, K. Stadius, Zahra Khonsari, Ilia Kempi, Toni Miilunpalo, Juha Inkinen, Vishnu Unnikrishnan, L. Anttila
{"title":"A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS","authors":"Yury Antonov, M. Valkama, M. Kosunen, J. Ryynänen, M. Zahra, K. Stadius, Zahra Khonsari, Ilia Kempi, Toni Miilunpalo, Juha Inkinen, Vishnu Unnikrishnan, L. Anttila","doi":"10.1109/ESSCIRC.2019.8902864","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902864","url":null,"abstract":"This paper proposes a wideband 2-5GHz LO phase-shifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering direct-conversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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