ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)最新文献_第6页

A 0.34-571nW All-Dynamic Versatile Sensor Interface for Temperature, Capacitance, and Resistance Sensing 一个0.34-571nW的全动态通用传感器接口，用于温度，电容和电阻传感

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902918

Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe

引用次数: 13

ESSCIRC 2019 TOC

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/esscirc.2019.8902508

引用次数: 0

A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration 用于低功耗无线3D集成的10.8pJ/bit脉冲位置感应收发器

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902754

B. Fletcher, T. Mak, Shidhartha Das

引用次数: 0

PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion 基于原位和PVT传感器融合的减小设计余量的puf密钥生成

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902733

Sachin Taneja, M. Alioto

{"title":"PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion","authors":"Sachin Taneja, M. Alioto","doi":"10.1109/ESSCIRC.2019.8902733","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902733","url":null,"abstract":"This work introduces a Physically Unclonable Function (PUF) based key generation scheme with run-time in-situ instability detection and process/voltage/temperature (PVT) sensors. Such sensors are fused to evaluate the sufficient number of correction bits NECC required by Error Correcting Code (ECC) to make the PUF output stable, and meet a given key error rate target. Run-time sensing overcomes the substantial ECC energy penalty associated with the traditional design-time margin of NECC for worst-case word, die, voltage and temperature. ECC with tunable NECC is introduced to enable energy saving in typical cases where NECC is lower than its worst-case value. Sensor fusion via simple linear regression estimates the required NECC at run-time.A testchip in 40 nm demonstrates the concept, based on a static monostable current mirror PUF with NECC = 0…4. Average energy reduction by 1.8X is shown compared to a traditional margined design, at an area overhead of less than 20%. As additional benefit of adjustable NECC, such energy savings can be further expanded under applications having less stringent stability requirements.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip 全集成半导体量子计算机片上系统的混合信号控制核心

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902885

Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina

{"title":"A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip","authors":"Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina","doi":"10.1109/ESSCIRC.2019.8902885","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902885","url":null,"abstract":"This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop 采用混合信号反馈环路的数字PWM和数字环路滤波器的d类放大器

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902785

M. Auer, Timuçin Karaca

引用次数: 1

A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit 一个2分接开关电容FFE发射机，在0.72-0.62 pJ/bit下实现1- 20gb /s

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902684

Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, E. Alon

引用次数: 0

2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications 2mb嵌入式相变存储器，具有16ns读访问时间和5mb /s写吞吐量的90纳米BCD技术，用于汽车应用

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902656

M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra

引用次数: 1

A 20F2 Area-Efficient Differential nand-Structured Physically Unclonable Function for Low-Cost IoT Security 面向低成本物联网安全的20F2区域高效差分结构物理不可克隆功能

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902680

Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee

引用次数: 0

A Hybrid THz Imaging System With a 100-Pixel CMOS Imager and a 3.25–3.50 THz Quantum Cascade Laser Frequency Comb 采用100像素CMOS成像仪和3.25-3.50太赫兹量子级联激光频率梳的混合太赫兹成像系统

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902823

Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta

{"title":"A Hybrid THz Imaging System With a 100-Pixel CMOS Imager and a 3.25–3.50 THz Quantum Cascade Laser Frequency Comb","authors":"Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta","doi":"10.1109/ESSCIRC.2019.8902823","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902823","url":null,"abstract":"The terahertz frequency range beyond 3 THz has exciting potential to have a transformative impact in a wide range of applications, including chemical and biomedical sensing, spectroscopy, imaging, and short-distance wireless communication. While there have been significant advancements in silicon-based THz imagers in the frequency ranges below 1 THz, technological development beyond 3 THz has been impeded by the lack of solid-state sources in this frequency range. In addition, the design space beyond 3 THz opens up fundamentally new challenges across electronics and the electromagnetic interface. In this spectral range, the wavelength is small enough (λox ≈ 50 μm at 3 THz) that a vertical via from the top antenna layer to the detector is a distributed element (transmission line or radiator). In this letter, we follow a careful circuits-electromagnetics co-design approach toward a hybrid imaging system with a 100-pixel CMOS imager that interfaces with a THz quantum cascade laser frequency comb that spans 3.25–3.5 THz with mode spacing of 17 GHz. The array chip, while designed for an optimal operation across 2.7–2.9 THz, demonstrates an average noise equivalent power (NEP) (across pixels) of $1260,{text{pW}}/sqrt {{text{Hz}}} $ between 3.25–3.5 THz and a projected NEP of $284,{text{pW}}/sqrt {{text{Hz}}} $ across the design range of 2.7–2.9 THz. To the best of our knowledge, we demonstrate for the first time full THz imaging in a hybrid quantum cascade laser (QCL)–CMOS fashion. This approach allows future works to leverage both QCL and CMOS technologies to demonstrate new technological advances for systems in the 1–10 THz range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4