Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane
{"title":"A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","authors":"Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane","doi":"10.1109/ESSCIRC.2019.8902523","DOIUrl":null,"url":null,"abstract":"This paper presents a low jitter performance and low power consumption injection-locked clock multiplier (ILCM) for IoT application in 65-nm CMOS. A transformer-based ultra-low power (ULP) LC-VCO is proposed to minimize the overall power consumption. The introduced capacitor feedback path boosts the VCO loop gain and thus a robust startup can be obtained. The proposed transformer-based VCO achieves −115.1 dBc/Hz at 1 MHz frequency offset with a 97 μW power consumption, which corresponds to a -194 dBc/Hz VCO figure-of-merit (FoM). Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while consuming 210 μW power. A -269 dB FoMJP of jitter and power is achieved by this proposed ILCM, and a -262 dB FoMJRP is obtained while considering the 520 MHz input reference with multiplication factor equals to 5.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902523","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a low jitter performance and low power consumption injection-locked clock multiplier (ILCM) for IoT application in 65-nm CMOS. A transformer-based ultra-low power (ULP) LC-VCO is proposed to minimize the overall power consumption. The introduced capacitor feedback path boosts the VCO loop gain and thus a robust startup can be obtained. The proposed transformer-based VCO achieves −115.1 dBc/Hz at 1 MHz frequency offset with a 97 μW power consumption, which corresponds to a -194 dBc/Hz VCO figure-of-merit (FoM). Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while consuming 210 μW power. A -269 dB FoMJP of jitter and power is achieved by this proposed ILCM, and a -262 dB FoMJRP is obtained while considering the 520 MHz input reference with multiplication factor equals to 5.